Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.02 95.02

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_usbdev 95.02 95.02



Module Instance : tb.dut.top_earlgrey.u_usbdev

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.02 95.02


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.02 95.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.73 90.65 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : usbdev
TotalCoveredPercent
Totals 74 70 94.59
Total Bits 402 382 95.02
Total Bits 0->1 201 191 95.02
Total Bits 1->0 201 191 95.02

Ports 74 70 94.59
Port Bits 402 382 95.02
Port Bits 0->1 201 191 95.02
Port Bits 1->0 201 191 95.02

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T3,T34 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T1,T3,T34 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T16,T17,T368 Yes T16,T17,T368 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T17,T368,T369 Yes T17,T368,T369 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T16,T17,T368 Yes T16,T17,T368 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T16,T17,T368 Yes T16,T17,T368 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T17,T53,T73 Yes T17,T53,T73 INPUT
tl_i.a_mask[3:0] Yes Yes T16,T17,T368 Yes T16,T17,T368 INPUT
tl_i.a_address[11:0] Yes Yes *T77,*T78,*T79 Yes T77,T78,T79 INPUT
tl_i.a_address[16:12] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T16,*T17,*T368 Yes T16,T17,T368 INPUT
tl_i.a_address[19:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T16,T17,T368 Yes T16,T17,T368 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T16,*T17,*T368 Yes T16,T17,T368 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T22,*T77,*T78 Yes T22,T77,T78 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T77,T78,T79 Yes T77,T78,T79 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T77,T78,T79 Yes T77,T78,T79 INPUT
tl_i.a_valid Yes Yes T16,T17,T368 Yes T16,T17,T368 INPUT
tl_o.a_ready Yes Yes T16,T17,T368 Yes T16,T17,T368 OUTPUT
tl_o.d_error Yes Yes T77,T78,T79 Yes T77,T78,T79 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T368,T369,T370 Yes T16,T368,T369 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T16,T368,T369 Yes T368,T369,T73 OUTPUT
tl_o.d_data[31:0] Yes Yes T16,T17,T368 Yes T17,T368,T369 OUTPUT
tl_o.d_sink Yes Yes T77,T78,T79 Yes T77,T78,T79 OUTPUT
tl_o.d_source[5:0] Yes Yes *T22,*T77,*T78 Yes T22,T77,T78 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T77,T78,T79 Yes T77,T78,T79 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T17,*T368,*T369 Yes T17,T368,T369 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T16,T17,T368 Yes T16,T17,T368 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T201,T192,T193 Yes T201,T192,T193 INPUT
alert_rx_i[0].ping_n Yes Yes T192,T193,T84 Yes T192,T193,T84 INPUT
alert_rx_i[0].ping_p Yes Yes T192,T193,T84 Yes T192,T193,T84 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T201,T192,T193 Yes T201,T192,T193 OUTPUT
cio_usb_dp_i Yes Yes T16,T7,T23 Yes T7,T23,T24 INPUT
cio_usb_dn_i Yes Yes T23,T24,T74 Yes T7,T23,T24 INPUT
usb_rx_d_i Yes Yes T23,T24,T74 Yes T23,T24,T74 INPUT
cio_usb_dp_o Yes Yes T16,T17,T53 Yes T17,T18,T19 OUTPUT
cio_usb_dp_en_o Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
cio_usb_dn_o Yes Yes T23,T24,T74 Yes T16,T73,T23 OUTPUT
cio_usb_dn_en_o Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
usb_tx_se0_o Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
usb_tx_d_o Yes Yes T16,T17,T53 Yes T17,T18,T19 OUTPUT
cio_sense_i Yes Yes T76,T169,T338 Yes T16,T73,T23 INPUT
usb_dp_pullup_o Yes Yes T17,T18,T19 Yes T17,T53,T73 OUTPUT
usb_dn_pullup_o Yes Yes T74,T75,T76 Yes T74,T75,T76 OUTPUT
usb_rx_enable_o Yes Yes T76,T167,T168 Yes T23,T24,T74 OUTPUT
usb_tx_use_d_se0_o Yes Yes T167,T168,T169 Yes T167,T168,T169 OUTPUT
usb_aon_suspend_req_o Yes Yes T17,T53,T18 Yes T17,T53,T18 OUTPUT
usb_aon_wake_ack_o Yes Yes T17,T53,T18 Yes T17,T53,T18 OUTPUT
usb_aon_bus_reset_i Yes Yes T74 Yes T74 INPUT
usb_aon_sense_lost_i Yes Yes T17,T53,T19 Yes T17,T53,T18 INPUT
usb_aon_wake_detect_active_i Yes Yes T17,T53,T19 Yes T17,T53,T18 INPUT
usb_ref_val_o Yes Yes T23,T24,T25 Yes T73,T23,T24 OUTPUT
usb_ref_pulse_o Yes Yes T73,T23,T24 Yes T73,T23,T24 OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
intr_pkt_received_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_pkt_sent_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_powered_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_disconnected_o Yes Yes T22,T299,T302 Yes T22,T299,T302 OUTPUT
intr_host_lost_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_link_reset_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_link_suspend_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_link_resume_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_av_out_empty_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_rx_full_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_av_overflow_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_link_in_err_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_link_out_err_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_rx_crc_err_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_rx_pid_err_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_rx_bitstuff_err_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_frame_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT
intr_av_setup_empty_o Yes Yes T299,T302,T303 Yes T299,T302,T303 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%