Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T43,T54,T44	Yes	T43,T54,T44	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T43,T54,T44	Yes	T43,T54,T44	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	INPUT
tl_i.a_valid	Yes	Yes	T43,T54,T65	Yes	T43,T54,T65	INPUT
tl_o.a_ready	Yes	Yes	T43,T54,T65	Yes	T43,T54,T65	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T54,T6,T172	Yes	T54,T6,T172	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T54,T65,T6	Yes	T43,T54,T65	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T54,T65,T6	Yes	T43,T54,T65	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T22,*T77,*T79	Yes	T22,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T54,*T6,*T172	Yes	T54,T6,T172	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T43,T54,T65	Yes	T43,T54,T65	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T107,T227	Yes	T65,T107,T227	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T65,T107,T117	Yes	T65,T117,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T65,T117,T84	Yes	T65,T107,T117	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T107,T227	Yes	T65,T107,T227	OUTPUT
cio_rx_i	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T54,T6,T172	Yes	T54,T6,T172	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T54,T172,T182	Yes	T54,T172,T182	OUTPUT
intr_rx_watermark_o	Yes	Yes	T54,T172,T182	Yes	T54,T172,T182	OUTPUT
intr_tx_empty_o	Yes	Yes	T54,T172,T182	Yes	T54,T172,T182	OUTPUT
intr_rx_overflow_o	Yes	Yes	T54,T172,T182	Yes	T54,T172,T182	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T43,T44,T6	Yes	T43,T44,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T43,T44,T6	Yes	T43,T44,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	INPUT
tl_i.a_valid	Yes	Yes	T43,T65,T44	Yes	T43,T65,T44	INPUT
tl_o.a_ready	Yes	Yes	T43,T65,T44	Yes	T43,T65,T44	OUTPUT
tl_o.d_error	Yes	Yes	T77,T79,T81	Yes	T77,T79,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T376,T41	Yes	T6,T376,T41	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T6,T376	Yes	T43,T65,T44	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T65,T6,T376	Yes	T43,T65,T44	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T79,T82	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T22,*T77,*T156	Yes	T22,T77,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T6,*T376,*T41	Yes	T6,T376,T41	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T43,T65,T44	Yes	T43,T65,T44	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T227,T117	Yes	T65,T227,T117	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T117,T84,T85	Yes	T117,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T117,T84,T85	Yes	T117,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T227,T117	Yes	T65,T227,T117	OUTPUT
cio_rx_i	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T6,T41,T42	Yes	T6,T41,T42	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_watermark_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_tx_empty_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_overflow_o	Yes	Yes	T306,T307,T308	Yes	T306,T307,T308	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	INPUT
tl_i.a_valid	Yes	Yes	T54,T65,T182	Yes	T54,T65,T182	INPUT
tl_o.a_ready	Yes	Yes	T54,T65,T182	Yes	T54,T65,T182	OUTPUT
tl_o.d_error	Yes	Yes	T77,T81,T112	Yes	T77,T81,T112	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T54,T65,T182	Yes	T54,T65,T182	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T54,T65,T182	Yes	T54,T65,T182	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T22,*T77,*T82	Yes	T22,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T81	Yes	T77,T81,T112	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T54,*T182,*T150	Yes	T54,T182,T150	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T54,T65,T182	Yes	T54,T65,T182	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T107,T117	Yes	T65,T107,T117	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T65,T107,T117	Yes	T65,T117,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T65,T117,T84	Yes	T65,T107,T117	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T107,T117	Yes	T65,T107,T117	OUTPUT
cio_rx_i	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	INPUT
cio_tx_o	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	OUTPUT
intr_rx_watermark_o	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	OUTPUT
intr_tx_empty_o	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	OUTPUT
intr_rx_overflow_o	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	INPUT
tl_i.a_valid	Yes	Yes	T65,T172,T309	Yes	T65,T172,T309	INPUT
tl_o.a_ready	Yes	Yes	T65,T172,T309	Yes	T65,T172,T309	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T79,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T172,T309	Yes	T65,T172,T309	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T65,T172,T309	Yes	T65,T172,T309	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T82,T156	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T22,*T77,*T79	Yes	T22,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T81	Yes	T77,T81,T112	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T172,*T309,*T310	Yes	T172,T309,T310	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T65,T172,T309	Yes	T65,T172,T309	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T84,T85	Yes	T65,T84,T85	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T84,T85	Yes	T65,T84,T85	OUTPUT
cio_rx_i	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	INPUT
cio_tx_o	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	OUTPUT
intr_rx_watermark_o	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	OUTPUT
intr_tx_empty_o	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	OUTPUT
intr_rx_overflow_o	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	INPUT
tl_i.a_valid	Yes	Yes	T65,T13,T14	Yes	T65,T13,T14	INPUT
tl_o.a_ready	Yes	Yes	T65,T13,T14	Yes	T65,T13,T14	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T81	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T65,T13,T14	Yes	T65,T13,T14	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T65,T13,T14	Yes	T65,T13,T14	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T22,*T77,*T156	Yes	T22,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T81	Yes	T77,T78,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T13,*T14,*T301	Yes	T13,T14,T301	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T65,T13,T14	Yes	T65,T13,T14	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T65,T677,T84	Yes	T65,T677,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T65,T677,T84	Yes	T65,T677,T84	OUTPUT
cio_rx_i	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	INPUT
cio_tx_o	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	OUTPUT
intr_rx_watermark_o	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	OUTPUT
intr_tx_empty_o	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	OUTPUT
intr_rx_overflow_o	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T299,T302,T303	Yes	T299,T302,T303	OUTPUT

*Tests covering at least one bit in the range