Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T64,T101,T201	Yes	T64,T101,T201	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T43,T44,T6	Yes	T43,T44,T6	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T43,T44,T6	Yes	T43,T44,T6	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T43,T65,T44	Yes	T43,T65,T44	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T43,T65,T44	Yes	T43,T65,T44	INPUT
tl_uart0_i.d_error	Yes	Yes	T77,T79,T81	Yes	T77,T79,T81	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T6,T376,T41	Yes	T6,T376,T41	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T65,T6,T376	Yes	T43,T65,T44	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T65,T6,T376	Yes	T43,T65,T44	INPUT
tl_uart0_i.d_sink	Yes	Yes	T77,T79,T82	Yes	T77,T78,T79	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T22,*T77,*T156	Yes	T22,T77,T79	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T6,*T376,*T41	Yes	T6,T376,T41	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T43,T65,T44	Yes	T43,T65,T44	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T54,T65,T182	Yes	T54,T65,T182	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T54,T65,T182	Yes	T54,T65,T182	INPUT
tl_uart1_i.d_error	Yes	Yes	T77,T81,T112	Yes	T77,T81,T112	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T54,T182,T150	Yes	T54,T182,T150	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T65,T182	Yes	T54,T65,T182	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T54,T65,T182	Yes	T54,T65,T182	INPUT
tl_uart1_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T22,*T77,*T82	Yes	T22,T77,T78	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T77,T78,T81	Yes	T77,T81,T112	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T54,*T182,*T150	Yes	T54,T182,T150	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T54,T65,T182	Yes	T54,T65,T182	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T65,T172,T309	Yes	T65,T172,T309	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T65,T172,T309	Yes	T65,T172,T309	INPUT
tl_uart2_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T79,T81	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T172,T309,T310	Yes	T172,T309,T310	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T65,T172,T309	Yes	T65,T172,T309	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T65,T172,T309	Yes	T65,T172,T309	INPUT
tl_uart2_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T82,T156	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T22,*T77,*T79	Yes	T22,T77,T78	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T77,T78,T81	Yes	T77,T81,T112	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T172,*T309,*T310	Yes	T172,T309,T310	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T65,T172,T309	Yes	T65,T172,T309	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T65,T13,T14	Yes	T65,T13,T14	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T65,T13,T14	Yes	T65,T13,T14	INPUT
tl_uart3_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T81	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T13,T14,T301	Yes	T13,T14,T301	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T65,T13,T14	Yes	T65,T13,T14	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T65,T13,T14	Yes	T65,T13,T14	INPUT
tl_uart3_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T22,*T77,*T156	Yes	T22,T77,T78	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T77,T78,T81	Yes	T77,T78,T81	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T13,*T14,*T301	Yes	T13,T14,T301	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T65,T13,T14	Yes	T65,T13,T14	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T180,T300,T181	Yes	T180,T300,T181	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T180,T300,T181	Yes	T180,T300,T181	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T65,T180,T300	Yes	T65,T180,T300	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T65,T180,T300	Yes	T65,T180,T300	INPUT
tl_i2c0_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T180,T300,T181	Yes	T180,T300,T181	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T65,T180,T300	Yes	T65,T180,T300	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T65,T180,T300	Yes	T65,T180,T300	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T77,*T113,*T156	Yes	T77,T78,T79	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T180,*T300,*T181	Yes	T180,T300,T181	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T65,T180,T300	Yes	T65,T180,T300	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T184,T300,T298	Yes	T184,T300,T298	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T184,T300,T298	Yes	T184,T300,T298	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T65,T184,T300	Yes	T65,T184,T300	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T65,T184,T300	Yes	T65,T184,T300	INPUT
tl_i2c1_i.d_error	Yes	Yes	T77,T78,T81	Yes	T77,T78,T81	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T184,T300,T298	Yes	T184,T300,T298	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T65,T184,T300	Yes	T65,T184,T300	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T65,T184,T300	Yes	T65,T184,T300	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T79	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	T77,*T156,*T404	Yes	T77,T78,T82	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T81	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T184,*T300,*T298	Yes	T184,T300,T298	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T65,T184,T300	Yes	T65,T184,T300	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T300,T313,T294	Yes	T300,T313,T294	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T300,T313,T294	Yes	T300,T313,T294	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T65,T300,T313	Yes	T65,T300,T313	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T65,T300,T313	Yes	T65,T300,T313	INPUT
tl_i2c2_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T300,T313,T294	Yes	T300,T313,T294	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T65,T300,T313	Yes	T65,T300,T313	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T65,T300,T313	Yes	T65,T300,T313	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T300,*T313,*T294	Yes	T300,T313,T294	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T65,T300,T313	Yes	T65,T300,T313	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T183,T185,T114	Yes	T183,T185,T114	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T183,T185,T114	Yes	T183,T185,T114	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T183,T185,T55	Yes	T183,T185,T55	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T183,T185,T55	Yes	T183,T185,T55	INPUT
tl_pattgen_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T183,T185,T114	Yes	T183,T185,T114	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T183,T185,T114	Yes	T183,T185,T55	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T183,T185,T114	Yes	T183,T185,T55	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T77,T79,*T156	Yes	T77,T78,T79	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T183,*T185,*T114	Yes	T183,T185,T114	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T183,T185,T55	Yes	T183,T185,T55	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T173,T46,T142	Yes	T173,T46,T142	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T173,T46,T142	Yes	T173,T46,T142	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T173,T46,T142	Yes	T173,T46,T142	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T173,T46,T142	Yes	T173,T46,T142	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T79,T81	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T173,T46,T142	Yes	T173,T46,T142	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T173,T46,T142	Yes	T173,T46,T142	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T173,T46,T142	Yes	T173,T46,T142	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T46,*T47,T77	Yes	T46,T47,T77	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T173,*T46,*T142	Yes	T173,T46,T142	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T173,T46,T142	Yes	T173,T46,T142	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T43,T44,T6	Yes	T43,T44,T6	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T300,T26,T28	Yes	T300,T26,T28	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T300,T26,T142	Yes	T300,T173,T15	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T300,T26,T142	Yes	T300,T173,T15	INPUT
tl_gpio_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T77,*T82,*T156	Yes	T77,T78,T79	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T34	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T38,T4,T72	Yes	T38,T4,T72	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T38,T4,T72	Yes	T38,T4,T72	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T38,T4,T72	Yes	T38,T4,T72	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T38,T4,T72	Yes	T38,T4,T72	INPUT
tl_spi_device_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T38,T4,T72	Yes	T38,T4,T72	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T38,T4,T72	Yes	T38,T4,T72	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T38,T4,T72	Yes	T38,T4,T72	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T22,*T77,*T113	Yes	T22,T77,T78	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T38,*T4,*T72	Yes	T38,T4,T72	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T38,T4,T72	Yes	T38,T4,T72	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T173,T238,T142	Yes	T173,T238,T142	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T173,T238,T142	Yes	T173,T238,T142	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T173,T238,T142	Yes	T173,T238,T142	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T173,T238,T142	Yes	T173,T238,T142	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T77,T79,T81	Yes	T77,T79,T81	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T238,T329,T22	Yes	T238,T329,T22	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T173,T238,T142	Yes	T173,T238,T142	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T173,T238,T142	Yes	T173,T238,T142	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T22,*T77,*T156	Yes	T22,T77,T78	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T173,*T238,*T142	Yes	T173,T238,T142	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T173,T238,T142	Yes	T173,T238,T142	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T77,T81,T112	Yes	T77,T79,T81	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T34,T59	Yes	T3,T34,T59	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T77,T79,T82	Yes	T77,T79,T156	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T46,*T47,*T77	Yes	T46,T47,T77	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T77,T81,T112	Yes	T77,T81,T112	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T3,*T43,*T34	Yes	T3,T43,T34	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T77,T79,T81	Yes	T77,T79,T81	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T43	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T3,T43	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T46,*T47,*T77	Yes	T46,T47,T77	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T54,T13	Yes	T3,T54,T13	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T3,T54,T13	Yes	T3,T54,T13	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T77,T79,T81	Yes	T77,T79,T81	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T54,T13,T172	Yes	T54,T13,T172	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T77,*T79,*T156	Yes	T80,T111,T709	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T77,T79,T81	Yes	T77,T79,T81	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T3,*T54,*T13	Yes	T3,T54,T13	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T77,T78,T81	Yes	T77,T78,T81	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T82	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T46,*T47,*T77	Yes	T46,T47,T77	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T81	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T72,*T80,*T111	Yes	T72,T80,T111	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T77,T81,T112	Yes	T77,T79,T81	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T2,T3,T38	Yes	T2,T3,T38	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T2,T3,T38	Yes	T3,T34,T5	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T77,T79,T113	Yes	T77,T78,T113	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T77,T78,T81	Yes	T77,T78,T81	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T2,T3,T38	Yes	T3,T34,T5	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T77,T78,T113	Yes	T77,T78,T113	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T77,T113,T82	Yes	T77,T113,T82	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T77,T78,T81	Yes	T77,T78,T79	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T38	Yes	T3,T34,T5	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T1,T43,T4	Yes	T1,T43,T4	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T1,T43,T4	Yes	T1,T43,T4	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T1,T43,T4	Yes	T1,T43,T4	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T1,T43,T4	Yes	T1,T43,T4	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T43,T4,T5	Yes	T43,T4,T5	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T60,T61	Yes	T5,T60,T61	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T1,T43,T4	Yes	T1,T43,T4	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T77,T78,T156	Yes	T77,T78,T79	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T70,*T188,*T189	Yes	T70,T188,T189	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T77,T78,T81	Yes	T77,T78,T79	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T43,T4	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T1,T43,T4	Yes	T1,T43,T4	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T77,T79,T81	Yes	T77,T79,T81	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T157,T158,T92	Yes	T157,T158,T92	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T157,T158,T92	Yes	T157,T158,T92	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T22,*T77,*T82	Yes	T22,T77,T78	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T79,T81	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T34	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T43,T59,T174	Yes	T43,T59,T174	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T43,T59,T174	Yes	T43,T59,T174	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T43,T59,T174	Yes	T43,T59,T174	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T43,T59,T174	Yes	T43,T59,T174	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T43,T59,T174	Yes	T43,T59,T174	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T43,T59,T174	Yes	T43,T59,T174	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T43,T59,T174	Yes	T43,T59,T174	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T77,*T78,*T156	Yes	T77,T78,T79	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T59,*T174,*T64	Yes	T43,T59,T174	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T43,T59,T174	Yes	T43,T59,T174	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T136,T137,T138	Yes	T136,T137,T138	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T41,T42	Yes	T43,T44,T6	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T6,T41,T42	Yes	T43,T44,T6	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T22,*T77,*T79	Yes	T22,T77,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T79,T81	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T136,*T137,*T138	Yes	T2,T136,T137	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T2,T43,T44	Yes	T2,T43,T44	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T3,T34	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T77,T79,T82	Yes	T77,T79,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T402,*T403,*T236	Yes	T402,T403,T236	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T77,T79,T82	Yes	T77,T79,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T77,T78,T81	Yes	T77,T78,T81	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T34,T59	Yes	T3,T34,T59	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T77,T78,T113	Yes	T77,T78,T79	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T77,*T82,*T156	Yes	T77,T78,T82	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T81	Yes	T77,T78,T79	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T3,*T43,*T34	Yes	T3,T43,T34	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T3,T43,T34	Yes	T3,T43,T34	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T34,T178,T120	Yes	T34,T178,T120	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T34,T178,T120	Yes	T34,T178,T120	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T34,T178,T120	Yes	T34,T178,T120	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T34,T178,T120	Yes	T34,T178,T120	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T34,T178,T120	Yes	T34,T178,T120	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T120,T17	Yes	T34,T120,T17	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T34,T178,T120	Yes	T34,T178,T120	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T22,*T77,*T156	Yes	T22,T77,T78	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T79,T81	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T34,*T120,*T17	Yes	T34,T178,T120	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T34,T178,T120	Yes	T34,T178,T120	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T17,T300,T53	Yes	T17,T300,T53	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T17,T300,T53	Yes	T17,T300,T53	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T17,T300,T53	Yes	T17,T300,T53	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T17,T300,T53	Yes	T17,T300,T53	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T77,T81,T112	Yes	T77,T81,T112	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T17,T300,T53	Yes	T17,T300,T53	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T300,T53	Yes	T17,T300,T53	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T17,T53,T142	Yes	T17,T300,T53	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T77,*T156,*T501	Yes	T77,T78,T79	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T77,T79,T81	Yes	T77,T78,T79	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T17,*T300,*T53	Yes	T17,T300,T53	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T17,T300,T53	Yes	T17,T300,T53	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T70,*T72,*T80	Yes	T70,T72,T80	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T46,T47,T22	Yes	T46,T47,T22	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T77,T78,T81	Yes	T77,T78,T81	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T77,T78,T82	Yes	T77,T82,T156	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T77,T78,*T82	Yes	T77,T82,T156	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T77,T78,T81	Yes	T77,T78,T81	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T77,*T78,*T112	Yes	T77,T78,T112	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range