Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T46,T47,T139
0	1	Covered	T139,T140,T285
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T139,T140,T285
1	Covered	T46,T47,T139

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T139,T140,T285
1	Covered	T46,T47,T139

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T139,T140,T285
1	1	Covered	T139,T140,T285

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T139
1	0	Covered	T139,T140,T285
1	1	Covered	T139,T140,T285

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T139,T140,T285

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T47,T139
0	Covered	T139,T140,T285

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T47,T139
0	Covered	T139,T140,T285

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	824808020	807242276	0	0
CheckNGreaterZero_A	1912	1912	0	0
GntImpliesReady_A	824808020	5410	0	0
GntImpliesValid_A	824808020	5410	0	0
GrantKnown_A	824808020	807242276	0	0
IdxKnown_A	824808020	807242276	0	0
IndexIsCorrect_A	824808020	5410	0	0
NoReadyValidNoGrant_A	824808020	0	0	0
Priority_A	824808020	5410	0	0
ReadyAndValidImplyGrant_A	824808020	5410	0	0
ReqAndReadyImplyGrant_A	824808020	5410	0	0
ReqImpliesValid_A	824808020	5410	0	0
ValidKnown_A	824808020	807242276	0	0
gen_data_port_assertion.DataFlow_A	824808020	5410	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	807242276	0	0
T1	880916	880574	0	0
T2	123230	123120	0	0
T3	386072	385846	0	0
T34	774402	774038	0	0
T38	261912	261802	0	0
T43	1370988	1370872	0	0
T54	241476	241466	0	0
T67	141872	141762	0	0
T87	166978	166868	0	0
T88	161862	161752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1912	1912	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T34	2	2	0	0
T38	2	2	0	0
T43	2	2	0	0
T54	2	2	0	0
T67	2	2	0	0
T87	2	2	0	0
T88	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	5410	0	0
T139	180256	1809	0	0
T140	205772	1805	0	0
T285	0	1796	0	0
T287	652360	0	0	0
T288	170506	0	0	0
T289	781020	0	0	0
T290	369902	0	0	0
T291	188262	0	0	0
T292	153468	0	0	0
T293	380622	0	0	0
T294	685734	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	5410	0	0
T139	180256	1809	0	0
T140	205772	1805	0	0
T285	0	1796	0	0
T287	652360	0	0	0
T288	170506	0	0	0
T289	781020	0	0	0
T290	369902	0	0	0
T291	188262	0	0	0
T292	153468	0	0	0
T293	380622	0	0	0
T294	685734	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	807242276	0	0
T1	880916	880574	0	0
T2	123230	123120	0	0
T3	386072	385846	0	0
T34	774402	774038	0	0
T38	261912	261802	0	0
T43	1370988	1370872	0	0
T54	241476	241466	0	0
T67	141872	141762	0	0
T87	166978	166868	0	0
T88	161862	161752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	807242276	0	0
T1	880916	880574	0	0
T2	123230	123120	0	0
T3	386072	385846	0	0
T34	774402	774038	0	0
T38	261912	261802	0	0
T43	1370988	1370872	0	0
T54	241476	241466	0	0
T67	141872	141762	0	0
T87	166978	166868	0	0
T88	161862	161752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	5410	0	0
T139	180256	1809	0	0
T140	205772	1805	0	0
T285	0	1796	0	0
T287	652360	0	0	0
T288	170506	0	0	0
T289	781020	0	0	0
T290	369902	0	0	0
T291	188262	0	0	0
T292	153468	0	0	0
T293	380622	0	0	0
T294	685734	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	5410	0	0
T139	180256	1809	0	0
T140	205772	1805	0	0
T285	0	1796	0	0
T287	652360	0	0	0
T288	170506	0	0	0
T289	781020	0	0	0
T290	369902	0	0	0
T291	188262	0	0	0
T292	153468	0	0	0
T293	380622	0	0	0
T294	685734	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	5410	0	0
T139	180256	1809	0	0
T140	205772	1805	0	0
T285	0	1796	0	0
T287	652360	0	0	0
T288	170506	0	0	0
T289	781020	0	0	0
T290	369902	0	0	0
T291	188262	0	0	0
T292	153468	0	0	0
T293	380622	0	0	0
T294	685734	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	5410	0	0
T139	180256	1809	0	0
T140	205772	1805	0	0
T285	0	1796	0	0
T287	652360	0	0	0
T288	170506	0	0	0
T289	781020	0	0	0
T290	369902	0	0	0
T291	188262	0	0	0
T292	153468	0	0	0
T293	380622	0	0	0
T294	685734	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	5410	0	0
T139	180256	1809	0	0
T140	205772	1805	0	0
T285	0	1796	0	0
T287	652360	0	0	0
T288	170506	0	0	0
T289	781020	0	0	0
T290	369902	0	0	0
T291	188262	0	0	0
T292	153468	0	0	0
T293	380622	0	0	0
T294	685734	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	807242276	0	0
T1	880916	880574	0	0
T2	123230	123120	0	0
T3	386072	385846	0	0
T34	774402	774038	0	0
T38	261912	261802	0	0
T43	1370988	1370872	0	0
T54	241476	241466	0	0
T67	141872	141762	0	0
T87	166978	166868	0	0
T88	161862	161752	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	824808020	5410	0	0
T139	180256	1809	0	0
T140	205772	1805	0	0
T285	0	1796	0	0
T287	652360	0	0	0
T288	170506	0	0	0
T289	781020	0	0	0
T290	369902	0	0	0
T291	188262	0	0	0
T292	153468	0	0	0
T293	380622	0	0	0
T294	685734	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T46,T47,T139
0	1	Covered	T139,T140,T285
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T139,T140,T285
1	Covered	T46,T47,T139

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T139,T140,T285
1	Covered	T46,T47,T139

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T139,T140,T285
1	1	Covered	T139,T140,T285

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T139
1	0	Covered	T139,T140,T285
1	1	Covered	T139,T140,T285

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T139,T140,T285

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T47,T139
0	Covered	T139,T140,T285

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T47,T139
0	Covered	T139,T140,T285

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412404010	403621138	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	412404010	4378	0	0
GntImpliesValid_A	412404010	4378	0	0
GrantKnown_A	412404010	403621138	0	0
IdxKnown_A	412404010	403621138	0	0
IndexIsCorrect_A	412404010	4378	0	0
NoReadyValidNoGrant_A	412404010	0	0	0
Priority_A	412404010	4378	0	0
ReadyAndValidImplyGrant_A	412404010	4378	0	0
ReqAndReadyImplyGrant_A	412404010	4378	0	0
ReqImpliesValid_A	412404010	4378	0	0
ValidKnown_A	412404010	403621138	0	0
gen_data_port_assertion.DataFlow_A	412404010	4378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	403621138	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	4378	0	0
T139	90128	1465	0	0
T140	102886	1461	0	0
T285	0	1452	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	4378	0	0
T139	90128	1465	0	0
T140	102886	1461	0	0
T285	0	1452	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	403621138	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	403621138	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	4378	0	0
T139	90128	1465	0	0
T140	102886	1461	0	0
T285	0	1452	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	4378	0	0
T139	90128	1465	0	0
T140	102886	1461	0	0
T285	0	1452	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	4378	0	0
T139	90128	1465	0	0
T140	102886	1461	0	0
T285	0	1452	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	4378	0	0
T139	90128	1465	0	0
T140	102886	1461	0	0
T285	0	1452	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	4378	0	0
T139	90128	1465	0	0
T140	102886	1461	0	0
T285	0	1452	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	403621138	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	4378	0	0
T139	90128	1465	0	0
T140	102886	1461	0	0
T285	0	1452	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T46,T47,T139
0	1	Covered	T139,T140,T285
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T139,T140,T285
1	Covered	T46,T47,T139

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T139,T140,T285
1	Covered	T46,T47,T139

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T139,T140,T285
1	1	Covered	T139,T140,T285

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T46,T47,T139
1	0	Covered	T139,T140,T285
1	1	Covered	T139,T140,T285

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T139,T140,T285

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T47,T139
0	Covered	T139,T140,T285

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T47,T139
0	Covered	T139,T140,T285

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412404010	403621138	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	412404010	1032	0	0
GntImpliesValid_A	412404010	1032	0	0
GrantKnown_A	412404010	403621138	0	0
IdxKnown_A	412404010	403621138	0	0
IndexIsCorrect_A	412404010	1032	0	0
NoReadyValidNoGrant_A	412404010	0	0	0
Priority_A	412404010	1032	0	0
ReadyAndValidImplyGrant_A	412404010	1032	0	0
ReqAndReadyImplyGrant_A	412404010	1032	0	0
ReqImpliesValid_A	412404010	1032	0	0
ValidKnown_A	412404010	403621138	0	0
gen_data_port_assertion.DataFlow_A	412404010	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	403621138	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T34	1	1	0	0
T38	1	1	0	0
T43	1	1	0	0
T54	1	1	0	0
T67	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	1032	0	0
T139	90128	344	0	0
T140	102886	344	0	0
T285	0	344	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	1032	0	0
T139	90128	344	0	0
T140	102886	344	0	0
T285	0	344	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	403621138	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	403621138	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	1032	0	0
T139	90128	344	0	0
T140	102886	344	0	0
T285	0	344	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	1032	0	0
T139	90128	344	0	0
T140	102886	344	0	0
T285	0	344	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	1032	0	0
T139	90128	344	0	0
T140	102886	344	0	0
T285	0	344	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	1032	0	0
T139	90128	344	0	0
T140	102886	344	0	0
T285	0	344	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	1032	0	0
T139	90128	344	0	0
T140	102886	344	0	0
T285	0	344	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	403621138	0	0
T1	440458	440287	0	0
T2	61615	61560	0	0
T3	193036	192923	0	0
T34	387201	387019	0	0
T38	130956	130901	0	0
T43	685494	685436	0	0
T54	120738	120733	0	0
T67	70936	70881	0	0
T87	83489	83434	0	0
T88	80931	80876	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412404010	1032	0	0
T139	90128	344	0	0
T140	102886	344	0	0
T285	0	344	0	0
T287	326180	0	0	0
T288	85253	0	0	0
T289	390510	0	0	0
T290	184951	0	0	0
T291	94131	0	0	0
T292	76734	0	0	0
T293	190311	0	0	0
T294	342867	0	0	0