Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	611329832	279633	0	0
DepthKnown_A	611329832	611237182	0	0
RvalidKnown_A	611329832	611237182	0	0
WreadyKnown_A	611329832	611237182	0	0
gen_passthru_fifo.paramCheckPass	11506	11506	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611329832	279633	0	0
T1	215162	78	0	0
T2	222194	211	0	0
T3	1932844	207	0	0
T4	298204	207	0	0
T5	1618662	218	0	0
T6	220816	78	0	0
T7	348706	16773	0	0
T8	339448	16708	0	0
T9	282582	7723	0	0
T10	295398	8515	0	0
T14	271480	100	0	0
T15	1075188	8692	0	0
T16	529436	1640	0	0
T17	806300	188	0	0
T38	421752	200	0	0
T39	447592	136	0	0
T40	554348	180	0	0
T103	391368	96	0	0
T104	884432	528	0	0
T105	345376	152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611329832	611237182	0	0
T1	1075810	1075700	0	0
T2	1110970	1110870	0	0
T3	9664220	9663050	0	0
T4	1491020	1490890	0	0
T5	8093310	8092140	0	0
T6	1104080	1103980	0	0
T7	697412	696700	0	0
T8	678896	678240	0	0
T9	565164	564464	0	0
T10	590796	590140	0	0
T14	407220	406518	0	0
T38	632628	631950	0	0
T39	671388	670644	0	0
T57	3794868	3794190	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611329832	611237182	0	0
T1	1075810	1075700	0	0
T2	1110970	1110870	0	0
T3	9664220	9663050	0	0
T4	1491020	1490890	0	0
T5	8093310	8092140	0	0
T6	1104080	1103980	0	0
T7	697412	696700	0	0
T8	678896	678240	0	0
T9	565164	564464	0	0
T10	590796	590140	0	0
T14	407220	406518	0	0
T38	632628	631950	0	0
T39	671388	670644	0	0
T57	3794868	3794190	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611329832	611237182	0	0
T1	1075810	1075700	0	0
T2	1110970	1110870	0	0
T3	9664220	9663050	0	0
T4	1491020	1490890	0	0
T5	8093310	8092140	0	0
T6	1104080	1103980	0	0
T7	697412	696700	0	0
T8	678896	678240	0	0
T9	565164	564464	0	0
T10	590796	590140	0	0
T14	407220	406518	0	0
T38	632628	631950	0	0
T39	671388	670644	0	0
T57	3794868	3794190	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11506	11506	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T5	10	10	0	0
T6	10	10	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0
T11	6	6	0	0
T12	6	6	0	0
T13	6	6	0	0
T31	6	6	0	0