Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8117675	0	0	0
DepthKnown_A	8117675	8115346	0	0
RvalidKnown_A	8117675	8115346	0	0
WreadyKnown_A	8117675	8115346	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8117675	0	0	0
DepthKnown_A	8117675	8115346	0	0
RvalidKnown_A	8117675	8115346	0	0
WreadyKnown_A	8117675	8115346	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8117675	42108	0	0
DepthKnown_A	8117675	8115346	0	0
RvalidKnown_A	8117675	8115346	0	0
WreadyKnown_A	8117675	8115346	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	42108	0	0
T1	107581	39	0	0
T2	111097	39	0	0
T3	966422	39	0	0
T4	149102	39	0	0
T5	809331	39	0	0
T6	110408	39	0	0
T7	174353	3314	0	0
T8	169724	3607	0	0
T9	141291	4935	0	0
T10	147699	5427	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8117675	74671	0	0
DepthKnown_A	8117675	8115346	0	0
RvalidKnown_A	8117675	8115346	0	0
WreadyKnown_A	8117675	8115346	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	74671	0	0
T1	107581	39	0	0
T2	111097	172	0	0
T3	966422	168	0	0
T4	149102	168	0	0
T5	809331	179	0	0
T6	110408	39	0	0
T7	174353	13459	0	0
T8	169724	13101	0	0
T9	141291	2788	0	0
T10	147699	3088	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8117675	8115346	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T7	174353	174175	0	0
T8	169724	169560	0	0
T9	141291	141116	0	0
T10	147699	147535	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	96476522	40336	0	0
DepthKnown_A	96476522	96462633	0	0
RvalidKnown_A	96476522	96462633	0	0
WreadyKnown_A	96476522	96462633	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	40336	0	0
T14	67870	25	0	0
T15	268797	2173	0	0
T16	132359	334	0	0
T17	201575	47	0	0
T38	105438	50	0	0
T39	111898	34	0	0
T40	138587	45	0	0
T103	97842	24	0	0
T104	221108	132	0	0
T105	86344	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	96476522	41091	0	0
DepthKnown_A	96476522	96462633	0	0
RvalidKnown_A	96476522	96462633	0	0
WreadyKnown_A	96476522	96462633	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	41091	0	0
T14	67870	25	0	0
T15	268797	2173	0	0
T16	132359	486	0	0
T17	201575	47	0	0
T38	105438	50	0	0
T39	111898	34	0	0
T40	138587	45	0	0
T103	97842	24	0	0
T104	221108	132	0	0
T105	86344	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	96476522	0	0	0
DepthKnown_A	96476522	96462633	0	0
RvalidKnown_A	96476522	96462633	0	0
WreadyKnown_A	96476522	96462633	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	96476522	0	0	0
DepthKnown_A	96476522	96462633	0	0
RvalidKnown_A	96476522	96462633	0	0
WreadyKnown_A	96476522	96462633	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	96476522	40336	0	0
DepthKnown_A	96476522	96462633	0	0
RvalidKnown_A	96476522	96462633	0	0
WreadyKnown_A	96476522	96462633	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	40336	0	0
T14	67870	25	0	0
T15	268797	2173	0	0
T16	132359	334	0	0
T17	201575	47	0	0
T38	105438	50	0	0
T39	111898	34	0	0
T40	138587	45	0	0
T103	97842	24	0	0
T104	221108	132	0	0
T105	86344	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	96476522	41091	0	0
DepthKnown_A	96476522	96462633	0	0
RvalidKnown_A	96476522	96462633	0	0
WreadyKnown_A	96476522	96462633	0	0
gen_passthru_fifo.paramCheckPass	1907	1907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	41091	0	0
T14	67870	25	0	0
T15	268797	2173	0	0
T16	132359	486	0	0
T17	201575	47	0	0
T38	105438	50	0	0
T39	111898	34	0	0
T40	138587	45	0	0
T103	97842	24	0	0
T104	221108	132	0	0
T105	86344	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96476522	96462633	0	0
T1	107581	107570	0	0
T2	111097	111087	0	0
T3	966422	966305	0	0
T4	149102	149089	0	0
T5	809331	809214	0	0
T6	110408	110398	0	0
T14	67870	67753	0	0
T38	105438	105325	0	0
T39	111898	111774	0	0
T57	632478	632365	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1907	1907	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T31	1	1	0	0