Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	65.00	50.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	537999354	236110	0	0
DepthKnown_A	537999354	537902674	0	0
RvalidKnown_A	537999354	537902674	0	0
WreadyKnown_A	537999354	537902674	0	0
gen_passthru_fifo.paramCheckPass	11500	11500	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	537999354	236110	0	0
T1	1987770	78	0	0
T2	1459408	78	0	0
T3	110070	78	0	0
T4	223948	193	0	0
T5	218152	196	0	0
T6	219050	78	0	0
T7	259592	10342	0	0
T8	349790	10026	0	0
T9	275418	7653	0	0
T10	335390	15895	0	0
T15	539352	996	0	0
T16	520836	2432	0	0
T17	852868	2320	0	0
T18	870960	222	0	0
T24	1024088	1908	0	0
T27	487692	1800	0	0
T39	557368	2336	0	0
T40	492552	252	0	0
T94	596684	340	0	0
T95	692796	272	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	537999354	537902674	0	0
T1	9938850	9937720	0	0
T2	7297040	7295870	0	0
T3	550350	549290	0	0
T4	1119740	1119630	0	0
T5	1090760	1090650	0	0
T6	1095250	1095140	0	0
T7	519184	518484	0	0
T8	699580	698908	0	0
T9	550836	550164	0	0
T10	670780	670068	0	0
T15	809028	808962	0	0
T16	781254	781194	0	0
T18	1306440	1305786	0	0
T40	738828	738168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	537999354	537902674	0	0
T1	9938850	9937720	0	0
T2	7297040	7295870	0	0
T3	550350	549290	0	0
T4	1119740	1119630	0	0
T5	1090760	1090650	0	0
T6	1095250	1095140	0	0
T7	519184	518484	0	0
T8	699580	698908	0	0
T9	550836	550164	0	0
T10	670780	670068	0	0
T15	809028	808962	0	0
T16	781254	781194	0	0
T18	1306440	1305786	0	0
T40	738828	738168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	537999354	537902674	0	0
T1	9938850	9937720	0	0
T2	7297040	7295870	0	0
T3	550350	549290	0	0
T4	1119740	1119630	0	0
T5	1090760	1090650	0	0
T6	1095250	1095140	0	0
T7	519184	518484	0	0
T8	699580	698908	0	0
T9	550836	550164	0	0
T10	670780	670068	0	0
T15	809028	808962	0	0
T16	781254	781194	0	0
T18	1306440	1305786	0	0
T40	738828	738168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11500	11500	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T5	10	10	0	0
T6	10	10	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0
T11	6	6	0	0
T12	6	6	0	0
T13	6	6	0	0
T14	6	6	0	0