Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.00	50.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	6618378	0	0	0
DepthKnown_A	6618378	6616003	0	0
RvalidKnown_A	6618378	6616003	0	0
WreadyKnown_A	6618378	6616003	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	6618378	0	0	0
DepthKnown_A	6618378	6616003	0	0
RvalidKnown_A	6618378	6616003	0	0
WreadyKnown_A	6618378	6616003	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	6618378	44079	0	0
DepthKnown_A	6618378	6616003	0	0
RvalidKnown_A	6618378	6616003	0	0
WreadyKnown_A	6618378	6616003	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	44079	0	0
T1	993885	39	0	0
T2	729704	39	0	0
T3	55035	39	0	0
T4	111974	39	0	0
T5	109076	39	0	0
T6	109525	39	0	0
T7	129796	2265	0	0
T8	174895	5884	0	0
T9	137709	4979	0	0
T10	167695	3330	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	6618378	66601	0	0
DepthKnown_A	6618378	6616003	0	0
RvalidKnown_A	6618378	6616003	0	0
WreadyKnown_A	6618378	6616003	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	66601	0	0
T1	993885	39	0	0
T2	729704	39	0	0
T3	55035	39	0	0
T4	111974	154	0	0
T5	109076	157	0	0
T6	109525	39	0	0
T7	129796	8077	0	0
T8	174895	4142	0	0
T9	137709	2674	0	0
T10	167695	12565	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6618378	6616003	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T7	129796	129621	0	0
T8	174895	174727	0	0
T9	137709	137541	0	0
T10	167695	167517	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85254307	30766	0	0
DepthKnown_A	85254307	85239777	0	0
RvalidKnown_A	85254307	85239777	0	0
WreadyKnown_A	85254307	85239777	0	0
gen_passthru_fifo.paramCheckPass	1906	1906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	30766	0	0
T15	134838	249	0	0
T16	130209	474	0	0
T17	213217	580	0	0
T18	217740	51	0	0
T24	256022	477	0	0
T27	121923	374	0	0
T39	139342	448	0	0
T40	123138	63	0	0
T94	149171	85	0	0
T95	173199	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906	1906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85254307	31949	0	0
DepthKnown_A	85254307	85239777	0	0
RvalidKnown_A	85254307	85239777	0	0
WreadyKnown_A	85254307	85239777	0	0
gen_passthru_fifo.paramCheckPass	1906	1906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	31949	0	0
T15	134838	249	0	0
T16	130209	742	0	0
T17	213217	580	0	0
T18	217740	60	0	0
T24	256022	477	0	0
T27	121923	526	0	0
T39	139342	720	0	0
T40	123138	63	0	0
T94	149171	85	0	0
T95	173199	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906	1906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85254307	0	0	0
DepthKnown_A	85254307	85239777	0	0
RvalidKnown_A	85254307	85239777	0	0
WreadyKnown_A	85254307	85239777	0	0
gen_passthru_fifo.paramCheckPass	1906	1906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906	1906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85254307	0	0	0
DepthKnown_A	85254307	85239777	0	0
RvalidKnown_A	85254307	85239777	0	0
WreadyKnown_A	85254307	85239777	0	0
gen_passthru_fifo.paramCheckPass	1906	1906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906	1906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85254307	30766	0	0
DepthKnown_A	85254307	85239777	0	0
RvalidKnown_A	85254307	85239777	0	0
WreadyKnown_A	85254307	85239777	0	0
gen_passthru_fifo.paramCheckPass	1906	1906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	30766	0	0
T15	134838	249	0	0
T16	130209	474	0	0
T17	213217	580	0	0
T18	217740	51	0	0
T24	256022	477	0	0
T27	121923	374	0	0
T39	139342	448	0	0
T40	123138	63	0	0
T94	149171	85	0	0
T95	173199	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906	1906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	85254307	31949	0	0
DepthKnown_A	85254307	85239777	0	0
RvalidKnown_A	85254307	85239777	0	0
WreadyKnown_A	85254307	85239777	0	0
gen_passthru_fifo.paramCheckPass	1906	1906	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	31949	0	0
T15	134838	249	0	0
T16	130209	742	0	0
T17	213217	580	0	0
T18	217740	60	0	0
T24	256022	477	0	0
T27	121923	526	0	0
T39	139342	720	0	0
T40	123138	63	0	0
T94	149171	85	0	0
T95	173199	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85254307	85239777	0	0
T1	993885	993772	0	0
T2	729704	729587	0	0
T3	55035	54929	0	0
T4	111974	111963	0	0
T5	109076	109065	0	0
T6	109525	109514	0	0
T15	134838	134827	0	0
T16	130209	130199	0	0
T18	217740	217631	0	0
T40	123138	123028	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906	1906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0