Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2505976	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28483881

1

T1

17397

T2

17325

T3

19774

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20844576	1			T1	8332		T2	8288		T3	9207
values[0x0]	8291217	1			T1	9065		T2	9037		T3	10567
values[0x1]	1854064	1			T1	1470		T2	1471		T3	1654

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	710502	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30279355

1

T1

18867

T2

18796

T3

21428

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14227458	1			T1	9434		T2	9398		T3	10714
valid_sources[0x01]	14227381	1			T1	9433		T2	9398		T3	10714
valid_sources[0x02]	40924	1			T73	1		T118	941		T851	402
valid_sources[0x03]	40583	1			T74	1		T118	822		T851	415
valid_sources[0x04]	40570	1			T73	1		T74	1		T118	698
valid_sources[0x05]	40346	1			T73	1		T118	734		T851	383
valid_sources[0x06]	40810	1			T73	2		T74	2		T118	766
valid_sources[0x07]	40508	1			T118	881		T851	392		T483	15
valid_sources[0x08]	40542	1			T5	12		T73	2		T118	749
valid_sources[0x09]	39862	1			T73	2		T118	777		T851	430
valid_sources[0x0a]	40474	1			T118	868		T851	358		T483	12
valid_sources[0x0b]	40847	1			T387	39		T118	776		T851	503
valid_sources[0x0c]	42835	1			T51	7		T118	851		T851	442
valid_sources[0x0d]	40568	1			T74	1		T206	4		T51	1
valid_sources[0x0e]	40599	1			T206	2		T118	814		T851	426
valid_sources[0x0f]	40850	1			T118	737		T851	429		T483	13
valid_sources[0x10]	40325	1			T206	4		T51	1		T118	824
valid_sources[0x11]	41622	1			T51	1		T118	844		T851	317
valid_sources[0x12]	40484	1			T73	1		T118	719		T851	449
valid_sources[0x13]	39974	1			T73	1		T74	5		T206	2
valid_sources[0x14]	40640	1			T73	1		T206	2		T51	1
valid_sources[0x15]	40405	1			T5	22		T73	1		T74	4
valid_sources[0x16]	40365	1			T73	2		T74	1		T51	1
valid_sources[0x17]	41878	1			T74	2		T118	734		T851	395
valid_sources[0x18]	40023	1			T73	1		T74	1		T118	663
valid_sources[0x19]	41413	1			T73	1		T74	2		T118	822
valid_sources[0x1a]	40263	1			T73	1		T118	867		T851	456
valid_sources[0x1b]	41089	1			T73	1		T74	1		T51	3
valid_sources[0x1c]	40102	1			T118	769		T851	393		T483	9
valid_sources[0x1d]	41219	1			T74	1		T206	2		T118	868
valid_sources[0x1e]	41229	1			T73	1		T118	721		T851	420
valid_sources[0x1f]	40756	1			T73	1		T118	752		T851	438
valid_sources[0x20]	41377	1			T118	756		T851	424		T483	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19987923

1

T1

8332

T2

8288

T3

9207

values[0x0]

all_enables

biggest_size

8260982

1

T1

9065

T2

9037

T3

10567

values[0x1]

all_enables

biggest_size

234976

1

T5

17

T73

18

T74

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2934702	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

463263

1

T69

13

T70

182

T71

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1152043	1			T69	33		T70	457		T71	44
values[0x0]	1096783	1			T69	8		T70	428		T71	33
values[0x1]	1149139	1			T69	47		T70	428		T71	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2271670	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1126295

1

T69

35

T70

436

T71

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52956	1			T69	1		T70	16		T111	10
valid_sources[0x01]	52061	1			T69	1		T70	18		T111	7
valid_sources[0x02]	52656	1			T70	23		T71	2		T484	1
valid_sources[0x03]	53568	1			T69	1		T70	19		T71	8
valid_sources[0x04]	51691	1			T69	3		T70	31		T111	4
valid_sources[0x05]	54148	1			T70	18		T484	5		T211	40
valid_sources[0x06]	53850	1			T70	31		T484	1		T211	20
valid_sources[0x07]	53332	1			T69	3		T70	12		T111	3
valid_sources[0x08]	53579	1			T69	3		T70	25		T111	6
valid_sources[0x09]	52612	1			T69	1		T70	16		T484	3
valid_sources[0x0a]	53519	1			T69	5		T70	28		T111	2
valid_sources[0x0b]	53734	1			T69	2		T70	25		T484	3
valid_sources[0x0c]	52536	1			T69	1		T70	19		T71	5
valid_sources[0x0d]	53780	1			T70	14		T111	5		T484	2
valid_sources[0x0e]	53287	1			T69	2		T70	22		T111	11
valid_sources[0x0f]	53778	1			T69	2		T70	36		T111	2
valid_sources[0x10]	54132	1			T69	7		T70	31		T111	5
valid_sources[0x11]	53241	1			T70	24		T71	1		T111	4
valid_sources[0x12]	52727	1			T69	1		T70	13		T71	2
valid_sources[0x13]	52407	1			T69	3		T70	32		T211	27
valid_sources[0x14]	54601	1			T69	2		T70	45		T71	2
valid_sources[0x15]	52675	1			T69	1		T70	18		T111	3
valid_sources[0x16]	53684	1			T69	1		T70	24		T71	27
valid_sources[0x17]	52328	1			T69	2		T70	24		T71	11
valid_sources[0x18]	53335	1			T69	3		T70	12		T111	9
valid_sources[0x19]	52776	1			T69	1		T70	20		T484	1
valid_sources[0x1a]	53243	1			T70	7		T71	22		T484	2
valid_sources[0x1b]	53956	1			T69	5		T70	29		T111	5
valid_sources[0x1c]	53889	1			T69	3		T70	17		T71	5
valid_sources[0x1d]	52978	1			T70	21		T484	2		T491	16
valid_sources[0x1e]	53550	1			T70	12		T111	5		T484	1
valid_sources[0x1f]	53604	1			T69	3		T70	21		T111	2
valid_sources[0x20]	53902	1			T69	1		T70	18		T484	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48395

1

T69

2

T70

21

T71

1

values[0x0]

all_enables

biggest_size

366245

1

T69

6

T70

133

T71

13

values[0x1]

all_enables

biggest_size

48623

1

T69

5

T70

28

T71

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3122352	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

507536

1

T69

10

T70

230

T71

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1241870	1			T69	41		T70	473		T71	50
values[0x0]	1144663	1			T69	10		T70	465		T71	42
values[0x1]	1243355	1			T69	43		T70	503		T71	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2396253	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1233635

1

T69

34

T70

541

T71

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56037	1			T69	1		T70	20		T111	1
valid_sources[0x01]	55855	1			T70	34		T71	8		T491	1
valid_sources[0x02]	55885	1			T69	2		T70	13		T111	3
valid_sources[0x03]	58096	1			T69	3		T70	14		T233	21
valid_sources[0x04]	55782	1			T69	4		T70	24		T111	9
valid_sources[0x05]	55135	1			T69	4		T70	32		T111	7
valid_sources[0x06]	56935	1			T70	11		T491	2		T211	10
valid_sources[0x07]	56426	1			T69	5		T70	9		T111	3
valid_sources[0x08]	57693	1			T69	3		T70	24		T71	1
valid_sources[0x09]	56763	1			T70	34		T491	5		T211	14
valid_sources[0x0a]	56819	1			T70	23		T491	1		T233	19
valid_sources[0x0b]	57148	1			T70	8		T71	1		T484	4
valid_sources[0x0c]	56449	1			T70	15		T484	9		T491	4
valid_sources[0x0d]	56313	1			T70	32		T491	4		T211	6
valid_sources[0x0e]	55353	1			T69	1		T70	30		T111	1
valid_sources[0x0f]	55939	1			T70	40		T111	3		T211	17
valid_sources[0x10]	57960	1			T69	2		T70	13		T111	1
valid_sources[0x11]	56103	1			T69	1		T70	35		T111	4
valid_sources[0x12]	55932	1			T69	1		T70	30		T111	3
valid_sources[0x13]	56529	1			T69	3		T70	7		T71	8
valid_sources[0x14]	55830	1			T69	6		T70	24		T71	9
valid_sources[0x15]	56616	1			T69	1		T70	35		T491	2
valid_sources[0x16]	57614	1			T69	4		T70	14		T111	12
valid_sources[0x17]	57211	1			T69	1		T70	24		T484	1
valid_sources[0x18]	56158	1			T70	22		T111	7		T484	2
valid_sources[0x19]	56629	1			T70	11		T484	24		T491	4
valid_sources[0x1a]	56482	1			T69	2		T70	62		T111	1
valid_sources[0x1b]	57447	1			T69	1		T70	15		T111	4
valid_sources[0x1c]	57114	1			T70	17		T484	13		T491	2
valid_sources[0x1d]	57072	1			T69	2		T71	1		T111	2
valid_sources[0x1e]	56572	1			T69	2		T70	10		T71	17
valid_sources[0x1f]	57610	1			T69	1		T70	22		T111	4
valid_sources[0x20]	57113	1			T70	32		T111	1		T491	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53407

1

T69

4

T70

24

T71

2

values[0x0]

all_enables

biggest_size

401144

1

T69

4

T70

178

T71

11

values[0x1]

all_enables

biggest_size

52985

1

T69

2

T70

28

T71

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2961193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

466982

1

T69

11

T70

169

T71

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1161105	1			T69	48		T70	387		T71	45
values[0x0]	1105584	1			T69	5		T70	402		T71	48
values[0x1]	1161486	1			T69	31		T70	401		T71	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2293106	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1135069

1

T69

39

T70

392

T71

51

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54040	1			T69	2		T70	12		T71	2
valid_sources[0x01]	53207	1			T70	16		T111	4		T484	2
valid_sources[0x02]	53128	1			T69	1		T70	13		T71	7
valid_sources[0x03]	54117	1			T69	2		T70	13		T71	1
valid_sources[0x04]	53157	1			T70	6		T71	6		T484	3
valid_sources[0x05]	53147	1			T70	22		T111	4		T484	7
valid_sources[0x06]	54224	1			T70	18		T71	2		T111	1
valid_sources[0x07]	53310	1			T69	2		T70	14		T71	5
valid_sources[0x08]	53192	1			T69	2		T70	24		T111	1
valid_sources[0x09]	53389	1			T69	1		T70	13		T71	3
valid_sources[0x0a]	53851	1			T69	2		T70	24		T111	3
valid_sources[0x0b]	53361	1			T69	2		T70	21		T71	1
valid_sources[0x0c]	52968	1			T70	15		T71	4		T484	5
valid_sources[0x0d]	53106	1			T69	1		T70	8		T71	5
valid_sources[0x0e]	53405	1			T69	1		T70	31		T111	1
valid_sources[0x0f]	54141	1			T70	19		T71	3		T111	3
valid_sources[0x10]	54128	1			T69	3		T70	15		T71	2
valid_sources[0x11]	54139	1			T70	19		T111	4		T484	1
valid_sources[0x12]	52636	1			T69	1		T70	15		T111	6
valid_sources[0x13]	54237	1			T69	3		T70	34		T111	4
valid_sources[0x14]	54197	1			T70	8		T71	2		T111	1
valid_sources[0x15]	52687	1			T69	2		T70	13		T71	5
valid_sources[0x16]	53627	1			T69	2		T70	17		T71	3
valid_sources[0x17]	53148	1			T69	1		T70	16		T71	3
valid_sources[0x18]	52968	1			T69	1		T70	26		T484	2
valid_sources[0x19]	53208	1			T69	1		T70	24		T71	1
valid_sources[0x1a]	53445	1			T69	5		T70	26		T111	3
valid_sources[0x1b]	53548	1			T69	1		T70	11		T111	1
valid_sources[0x1c]	53410	1			T70	16		T111	2		T484	2
valid_sources[0x1d]	54416	1			T69	1		T70	21		T71	8
valid_sources[0x1e]	54324	1			T69	3		T70	32		T71	5
valid_sources[0x1f]	54010	1			T69	1		T70	20		T71	3
valid_sources[0x20]	53180	1			T69	1		T70	16		T71	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49268

1

T69

6

T70

18

T71

4

values[0x0]

all_enables

biggest_size

368743

1

T69

2

T70

141

T71

20

values[0x1]

all_enables

biggest_size

48971

1

T69

3

T70

10

T71

2