Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : kmac
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.92 98.92

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_kmac 99.94 99.94


Module Instance : tb.dut.top_earlgrey.u_kmac

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.94 99.94


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.94 99.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.73 90.65 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : kmac
TotalCoveredPercent
Totals 76 71 93.42
Total Bits 6506 6436 98.92
Total Bits 0->1 3253 3219 98.95
Total Bits 1->0 3253 3217 98.89

Ports 76 71 93.42
Port Bits 6506 6436 98.92
Port Bits 0->1 3253 3219 98.95
Port Bits 1->0 3253 3217 98.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_shadowed_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_edn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_edn_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T393,T394,T210 Yes T393,T394,T210 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T135,T116,T104 Yes T135,T116,T104 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T135,T116,T104 Yes T135,T116,T104 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T393,T394,T210 Yes T393,T394,T210 INPUT
tl_i.a_mask[3:0] Yes Yes T135,T116,T104 Yes T135,T116,T104 INPUT
tl_i.a_address[11:0] Yes Yes *T69,*T70,*T71 Yes T69,T70,T71 INPUT
tl_i.a_address[16:12] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T135,*T116,*T104 Yes T135,T116,T104 INPUT
tl_i.a_address[19:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T135,*T116,*T104 Yes T135,T116,T104 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T135,*T116,*T104 Yes T135,T116,T104 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T135,*T116,*T104 Yes T135,T116,T104 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T69,*T70,*T71 Yes T69,T70,T71 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T393,T394,T210 Yes T393,T394,T210 INPUT
tl_i.a_valid Yes Yes T135,T116,T104 Yes T135,T116,T104 INPUT
tl_o.a_ready Yes Yes T135,T116,T104 Yes T135,T116,T104 OUTPUT
tl_o.d_error Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T116,T104,T393 Yes T135,T116,T104 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T135,T116,T104 Yes T135,T116,T104 OUTPUT
tl_o.d_data[31:0] Yes Yes T135,T116,T393 Yes T135,T393,T394 OUTPUT
tl_o.d_sink Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_source[5:0] Yes Yes *T69,*T70,*T71 Yes T69,T70,T71 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T116,*T393,*T394 Yes T393,T394,T210 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T135,T116,T104 Yes T135,T116,T104 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T204,T75,T76 Yes T204,T75,T76 INPUT
alert_rx_i[0].ping_n Yes Yes T204,T75,T76 Yes T204,T75,T76 INPUT
alert_rx_i[0].ping_p Yes Yes T204,T75,T76 Yes T204,T75,T76 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ping_n Yes Yes T204,T75,T76 Yes T204,T75,T76 INPUT
alert_rx_i[1].ping_p Yes Yes T204,T75,T76 Yes T204,T75,T76 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T204,T75,T76 Yes T204,T75,T76 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_key_i.key[0][23:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][24] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][51:25] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][52] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][60:53] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][61] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][62] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][63] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][92:64] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][93] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][194:94] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][195] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][196] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][197] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][202:198] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][203] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][210:204] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][211] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][255:212] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][18:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][19] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][51:20] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][52] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][62:53] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][63] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][106:64] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][107] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][159:108] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][160] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][210:161] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][211] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][245:212] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][246] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][255:247] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.valid Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
app_i[0].last Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
app_i[0].strb[7:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
app_i[0].data[63:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
app_i[0].valid Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
app_i[1].last Yes Yes T6,T56,T58 Yes T6,T56,T58 INPUT
app_i[1].strb[7:0] Yes Yes T6,T56,T58 Yes T6,T56,T58 INPUT
app_i[1].data[63:0] Yes Yes T6,T56,T58 Yes T6,T56,T58 INPUT
app_i[1].valid Yes Yes T6,T56,T58 Yes T6,T56,T58 INPUT
app_i[2].last Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
app_i[2].strb[7:0] No No No INPUT
app_i[2].data[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
app_i[2].data[63:39] No No No INPUT
app_i[2].valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
app_o[0].error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
app_o[0].digest_share1[383:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 OUTPUT
app_o[0].digest_share0[383:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 OUTPUT
app_o[0].done Yes Yes T116,T117,T210 Yes T116,T117,T210 OUTPUT
app_o[0].ready Yes Yes T116,T117,T210 Yes T116,T117,T210 OUTPUT
app_o[1].error No No No OUTPUT
app_o[1].digest_share1[383:0] Yes Yes T6,T56,T57 Yes T6,T56,T57 OUTPUT
app_o[1].digest_share0[383:0] Yes Yes T6,T57,T175 Yes T6,T57,T175 OUTPUT
app_o[1].done Yes Yes T6,T56,T58 Yes T6,T56,T58 OUTPUT
app_o[1].ready Yes Yes T6,T56,T58 Yes T6,T56,T58 OUTPUT
app_o[2].error No No Yes T138,T139,T140 OUTPUT
app_o[2].digest_share1[383:0] Yes Yes T102,T134,T136 Yes T102,T134,T136 OUTPUT
app_o[2].digest_share0[383:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
app_o[2].done Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
app_o[2].ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
entropy_o.edn_req Yes Yes T393,T222,T395 Yes T393,T222,T395 OUTPUT
entropy_i.edn_bus[31:0] Yes Yes T393,T222,T395 Yes T393,T222,T395 INPUT
entropy_i.edn_fips No No Yes T222,T395,T150 INPUT
entropy_i.edn_ack Yes Yes T393,T222,T395 Yes T393,T222,T395 INPUT
lc_escalate_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
intr_kmac_done_o Yes Yes T119,T120,T121 Yes T119,T120,T121 OUTPUT
intr_fifo_empty_o Yes Yes T119,T120,T121 Yes T119,T120,T121 OUTPUT
intr_kmac_err_o Yes Yes T119,T120,T121 Yes T119,T120,T121 OUTPUT
en_masking_o Unreachable Unreachable Unreachable OUTPUT
idle_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_kmac
TotalCoveredPercent
Totals 75 72 96.00
Total Bits 6440 6436 99.94
Total Bits 0->1 3220 3219 99.97
Total Bits 1->0 3220 3217 99.91

Ports 75 72 96.00
Port Bits 6440 6436 99.94
Port Bits 0->1 3220 3219 99.97
Port Bits 1->0 3220 3217 99.91

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_shadowed_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_edn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_edn_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T393,T394,T210 Yes T393,T394,T210 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T135,T116,T104 Yes T135,T116,T104 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T135,T116,T104 Yes T135,T116,T104 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T393,T394,T210 Yes T393,T394,T210 INPUT
tl_i.a_mask[3:0] Yes Yes T135,T116,T104 Yes T135,T116,T104 INPUT
tl_i.a_address[11:0] Yes Yes *T69,*T70,*T71 Yes T69,T70,T71 INPUT
tl_i.a_address[16:12] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T135,*T116,*T104 Yes T135,T116,T104 INPUT
tl_i.a_address[19:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T135,*T116,*T104 Yes T135,T116,T104 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T135,*T116,*T104 Yes T135,T116,T104 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T135,*T116,*T104 Yes T135,T116,T104 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T69,*T70,*T71 Yes T69,T70,T71 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T393,T394,T210 Yes T393,T394,T210 INPUT
tl_i.a_valid Yes Yes T135,T116,T104 Yes T135,T116,T104 INPUT
tl_o.a_ready Yes Yes T135,T116,T104 Yes T135,T116,T104 OUTPUT
tl_o.d_error Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T116,T104,T393 Yes T135,T116,T104 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T135,T116,T104 Yes T135,T116,T104 OUTPUT
tl_o.d_data[31:0] Yes Yes T135,T116,T393 Yes T135,T393,T394 OUTPUT
tl_o.d_sink Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_source[5:0] Yes Yes *T69,*T70,*T71 Yes T69,T70,T71 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T116,*T393,*T394 Yes T393,T394,T210 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T135,T116,T104 Yes T135,T116,T104 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T204,T75,T76 Yes T204,T75,T76 INPUT
alert_rx_i[0].ping_n Yes Yes T204,T75,T76 Yes T204,T75,T76 INPUT
alert_rx_i[0].ping_p Yes Yes T204,T75,T76 Yes T204,T75,T76 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ping_n Yes Yes T204,T75,T76 Yes T204,T75,T76 INPUT
alert_rx_i[1].ping_p Yes Yes T204,T75,T76 Yes T204,T75,T76 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T204,T75,T76 Yes T204,T75,T76 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_key_i.key[0][23:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][24] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][51:25] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][52] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][60:53] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][61] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][62] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][63] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][92:64] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][93] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][194:94] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][195] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][196] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][197] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][202:198] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][203] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][210:204] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][211] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[0][255:212] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][18:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][19] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][51:20] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][52] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][62:53] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][63] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][106:64] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][107] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][159:108] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][160] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][210:161] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][211] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][245:212] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][246] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.key[1][255:247] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
keymgr_key_i.valid Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
app_i[0].last Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
app_i[0].strb[7:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
app_i[0].data[63:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
app_i[0].valid Yes Yes T116,T117,T210 Yes T116,T117,T210 INPUT
app_i[1].last Yes Yes T6,T56,T58 Yes T6,T56,T58 INPUT
app_i[1].strb[7:0] Yes Yes T6,T56,T58 Yes T6,T56,T58 INPUT
app_i[1].data[63:0] Yes Yes T6,T56,T58 Yes T6,T56,T58 INPUT
app_i[1].valid Yes Yes T6,T56,T58 Yes T6,T56,T58 INPUT
app_i[2].last Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
app_i[2].strb[7:0] Excluded Excluded Excluded INPUT [UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
app_i[2].data[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
app_i[2].data[63:39] Excluded Excluded Excluded INPUT [UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
app_i[2].valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
app_o[0].error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
app_o[0].digest_share1[383:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 OUTPUT
app_o[0].digest_share0[383:0] Yes Yes T116,T117,T210 Yes T116,T117,T210 OUTPUT
app_o[0].done Yes Yes T116,T117,T210 Yes T116,T117,T210 OUTPUT
app_o[0].ready Yes Yes T116,T117,T210 Yes T116,T117,T210 OUTPUT
app_o[1].error No No No OUTPUT
app_o[1].digest_share1[383:0] Yes Yes T6,T56,T57 Yes T6,T56,T57 OUTPUT
app_o[1].digest_share0[383:0] Yes Yes T6,T57,T175 Yes T6,T57,T175 OUTPUT
app_o[1].done Yes Yes T6,T56,T58 Yes T6,T56,T58 OUTPUT
app_o[1].ready Yes Yes T6,T56,T58 Yes T6,T56,T58 OUTPUT
app_o[2].error No No Yes T138,T139,T140 OUTPUT
app_o[2].digest_share1[383:0] Yes Yes T102,T134,T136 Yes T102,T134,T136 OUTPUT
app_o[2].digest_share0[383:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
app_o[2].done Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
app_o[2].ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
entropy_o.edn_req Yes Yes T393,T222,T395 Yes T393,T222,T395 OUTPUT
entropy_i.edn_bus[31:0] Yes Yes T393,T222,T395 Yes T393,T222,T395 INPUT
entropy_i.edn_fips No No Yes T222,T395,T150 INPUT
entropy_i.edn_ack Yes Yes T393,T222,T395 Yes T393,T222,T395 INPUT
lc_escalate_en_i[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
intr_kmac_done_o Yes Yes T119,T120,T121 Yes T119,T120,T121 OUTPUT
intr_fifo_empty_o Yes Yes T119,T120,T121 Yes T119,T120,T121 OUTPUT
intr_kmac_err_o Yes Yes T119,T120,T121 Yes T119,T120,T121 OUTPUT
en_masking_o Unreachable Unreachable Unreachable OUTPUT
idle_o[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%