Unified Coverage Report :: Module

Line Coverage for Module : pinmux

	Line No.	Total	Covered	Percent
TOTAL		1147	884	77.07
CONT_ASSIGN	127	1	1	100.00
ALWAYS	156	41	41	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	237	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	0	0.00
CONT_ASSIGN	238	1	0	0.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	239	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	240	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	245	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	260	1	1	100.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	263	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	264	1	0	0.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	306	0	0
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
ALWAYS	408	15	15	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	481	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	0	0.00
CONT_ASSIGN	513	1	0	0.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	524	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	567	1	0	0.00
CONT_ASSIGN	567	1	0	0.00
CONT_ASSIGN	567	1	0	0.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	567	1	0	0.00
CONT_ASSIGN	567	1	0	0.00
CONT_ASSIGN	571	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
127	1	1
156	1	1
157	1	1
158	1	1
161	1	1
162	1	1
163	1	1
			MISSING_ELSE
165	1	1
166	1	1
			MISSING_ELSE
168	1	1
169	1	1
			MISSING_ELSE
171	1	1
172	1	1
			MISSING_ELSE
174	1	1
175	1	1
			MISSING_ELSE
177	1	1
178	1	1
			MISSING_ELSE
180	1	1
181	1	1
			MISSING_ELSE
183	1	1
184	1	1
			MISSING_ELSE
186	1	1
187	1	1
			MISSING_ELSE
191	1	1
192	1	1
193	1	1
			MISSING_ELSE
195	1	1
196	1	1
			MISSING_ELSE
198	1	1
199	1	1
			MISSING_ELSE
201	1	1
202	1	1
			MISSING_ELSE
204	1	1
205	1	1
			MISSING_ELSE
207	1	1
208	1	1
			MISSING_ELSE
210	1	1
211	1	1
			MISSING_ELSE
213	1	1
214	1	1
			MISSING_ELSE
216	1	1
217	1	1
			MISSING_ELSE
237	16	16
238	14	16
239	0	16
240	0	16
241	0	16
242	0	16
243	16	16
244	16	16
245	14	16
246	16	16
259	47	47
260	47	47
261	0	47
262	0	47
263	0	47
264	0	47
265	47	47
266	47	47
267	47	47
268	47	47
306		unreachable
307	1	1
405	1	1
408	1	1
409	1	1
410	1	1
411	1	1
412	1	1
413	1	1
415	1	1
418	1	1
419	1	1
420	1	1
421	1	1
			MISSING_ELSE
426	1	1
427	1	1
428	1	1
429	1	1
			MISSING_ELSE
445	1	1
449	57	57
459	1	1
460	1	1
464	47	47
468	47	47
477	47	47
481	47	47
486	47	47
488	47	47
496	1	1
500	16	16
504	16	16
513	14	16
517	16	16
522	16	16
524	16	16
536	1	1
541	1	1
546	8	8
567	3	8
571	1	1

Cond Coverage for Module : pinmux

	Total	Covered	Percent
Conditions	1975	1568	79.39
Logical	1975	1568	79.39
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
127-477	88.37
477-481	74.67
481	72.94
481-517	85.08
517-546	75.22

Toggle Coverage for Module : pinmux

	Total	Covered	Percent
Totals	649	329	50.69
Total Bits	2940	1914	65.10
Total Bits 0->1	1470	958	65.17
Total Bits 1->0	1470	956	65.03


Ports	649	329	50.69
Port Bits	2940	1914	65.10
Port Bits 0->1	1470	958	65.17
Port Bits 1->0	1470	956	65.03

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_sys_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pin_wkup_req_o	Yes	Yes	T16,T14,T17	Yes	T16,T14,T17	OUTPUT
usb_wkup_req_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
sleep_en_i	Yes	Yes	T1,T2,T3	Yes	T55,T4,T5	INPUT
strap_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
strap_en_override_i	Unreachable	Unreachable		Unreachable		INPUT
lc_dft_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T6,T56,T57	Yes	T6,T56,T58	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pinmux_hw_debug_en_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dft_strap_test_o.straps[1:0]	No	No		Yes	T59,T60,T61	OUTPUT
dft_strap_test_o.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dft_hold_tap_sel_i	Unreachable	Unreachable		Unreachable		INPUT
lc_jtag_o.tdi	Yes	Yes	T6,T56,T58	Yes	T6,T56,T58	OUTPUT
lc_jtag_o.trst_n	Yes	Yes	T6,T56,T57	Yes	T6,T56,T58	OUTPUT
lc_jtag_o.tms	Yes	Yes	T6,T56,T58	Yes	T6,T56,T58	OUTPUT
lc_jtag_o.tck	Yes	Yes	T6,T56,T58	Yes	T6,T56,T58	OUTPUT
lc_jtag_i.tdo_oe	Yes	Yes	T6,T56,T58	Yes	T6,T56,T58	INPUT
lc_jtag_i.tdo	Yes	Yes	T6,T56,T58	Yes	T6,T56,T58	INPUT
rv_jtag_o.tdi	Yes	Yes	T5,T62,T63	Yes	T5,T62,T63	OUTPUT
rv_jtag_o.trst_n	Yes	Yes	T5,T64,T59	Yes	T5,T62,T63	OUTPUT
rv_jtag_o.tms	Yes	Yes	T5,T62,T63	Yes	T5,T62,T63	OUTPUT
rv_jtag_o.tck	Yes	Yes	T5,T62,T63	Yes	T5,T62,T63	OUTPUT
rv_jtag_i.tdo_oe	Yes	Yes	T5,T62,T63	Yes	T5,T62,T63	INPUT
rv_jtag_i.tdo	Yes	Yes	T5,T62,T63	Yes	T5,T62,T63	INPUT
dft_jtag_o.tdi	Yes	Yes	T64,T59,T65	Yes	T64,T59,T65	OUTPUT
dft_jtag_o.trst_n	Yes	Yes	T64,T59,T65	Yes	T64,T59,T65	OUTPUT
dft_jtag_o.tms	Yes	Yes	T64,T59,T65	Yes	T64,T59,T65	OUTPUT
dft_jtag_o.tck	Yes	Yes	T64,T59,T65	Yes	T64,T59,T65	OUTPUT
dft_jtag_i.tdo_oe	Yes	Yes	T64,T59,T65	Yes	T64,T59,T65	INPUT
dft_jtag_i.tdo	Yes	Yes	T64,T59,T65	Yes	T64,T59,T65	INPUT
usbdev_dppullup_en_i	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
usbdev_dnpullup_en_i	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	INPUT
usb_dppullup_en_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
usb_dnpullup_en_o	Yes	Yes	T66,T67,T68	Yes	T66,T67,T68	OUTPUT
usbdev_suspend_req_i	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
usbdev_wake_ack_i	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
usbdev_bus_reset_o	Yes	Yes	T67	Yes	T67	OUTPUT
usbdev_sense_lost_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
usbdev_wake_detect_active_o	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[11:0]	Yes	Yes	T69,T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:17]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T5,T63,*T72	Yes	T5,T63,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T73,T74	Yes	T5,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T51,T69,*T70	Yes	T51,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T76,T52	Yes	T75,T76,T52	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T76,T52	Yes	T75,T76,T52	OUTPUT
periph_to_mio_i[74:0]	Yes	Yes	T25,T26,T27	Yes	T14,T25,T26	INPUT
periph_to_mio_oe_i[74:0]	Yes	Yes	T25,T27,T28	Yes	T14,T25,T26	INPUT
mio_to_periph_o[56:0]	Yes	Yes	T14,T25,T26	Yes	T14,T25,T26	OUTPUT
periph_to_dio_i[11:0]	Yes	Yes	T16,T17,*T18	Yes	T16,T17,T18	INPUT
periph_to_dio_i[13:12]	No	No		No		INPUT
periph_to_dio_i[15:14]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
periph_to_dio_oe_i[15:0]	Yes	Yes	T22,T23,T24	Yes	T22,T23,T24	INPUT
dio_to_periph_o[15:0]	Yes	Yes	T78,T22,T23	Yes	T22,T23,T24	OUTPUT
mio_attr_o[0].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[0].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[0].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[0].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[0].keep_en	No	No		No		OUTPUT
mio_attr_o[0].schmitt_en	No	No		No		OUTPUT
mio_attr_o[0].od_en	No	No		No		OUTPUT
mio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[0].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[0].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[1].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[1].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[1].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[1].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[1].keep_en	No	No		No		OUTPUT
mio_attr_o[1].schmitt_en	No	No		No		OUTPUT
mio_attr_o[1].od_en	No	No		No		OUTPUT
mio_attr_o[1].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[1].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[1].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[2].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[2].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[2].pull_en	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
mio_attr_o[2].pull_select	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
mio_attr_o[2].keep_en	No	No		No		OUTPUT
mio_attr_o[2].schmitt_en	No	No		No		OUTPUT
mio_attr_o[2].od_en	No	No		No		OUTPUT
mio_attr_o[2].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[2].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[2].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[3].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[3].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[3].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[3].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[3].keep_en	No	No		No		OUTPUT
mio_attr_o[3].schmitt_en	No	No		No		OUTPUT
mio_attr_o[3].od_en	No	No		No		OUTPUT
mio_attr_o[3].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[3].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[3].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[4].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[4].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[4].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[4].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[4].keep_en	No	No		No		OUTPUT
mio_attr_o[4].schmitt_en	No	No		No		OUTPUT
mio_attr_o[4].od_en	No	No		No		OUTPUT
mio_attr_o[4].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[4].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[4].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[5].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[5].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[5].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[5].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[5].keep_en	No	No		No		OUTPUT
mio_attr_o[5].schmitt_en	No	No		No		OUTPUT
mio_attr_o[5].od_en	No	No		No		OUTPUT
mio_attr_o[5].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[5].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[5].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[6].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[6].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[6].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[6].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[6].keep_en	No	No		No		OUTPUT
mio_attr_o[6].schmitt_en	No	No		No		OUTPUT
mio_attr_o[6].od_en	No	No		No		OUTPUT
mio_attr_o[6].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[6].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[6].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[7].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[7].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[7].pull_en	Yes	Yes	T29,T30,T31	Yes	T33,T34,T35	OUTPUT
mio_attr_o[7].pull_select	Yes	Yes	T29,T30,T31	Yes	T33,T34,T35	OUTPUT
mio_attr_o[7].keep_en	No	No		No		OUTPUT
mio_attr_o[7].schmitt_en	No	No		No		OUTPUT
mio_attr_o[7].od_en	No	No		No		OUTPUT
mio_attr_o[7].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[7].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[7].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[8].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[8].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[8].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[8].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[8].keep_en	No	No		No		OUTPUT
mio_attr_o[8].schmitt_en	No	No		No		OUTPUT
mio_attr_o[8].od_en	No	No		No		OUTPUT
mio_attr_o[8].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[8].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[8].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[9].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[9].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[9].pull_en	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
mio_attr_o[9].pull_select	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
mio_attr_o[9].keep_en	No	No		No		OUTPUT
mio_attr_o[9].schmitt_en	No	No		No		OUTPUT
mio_attr_o[9].od_en	No	No		No		OUTPUT
mio_attr_o[9].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[9].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[9].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[10].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[10].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[10].pull_en	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
mio_attr_o[10].pull_select	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
mio_attr_o[10].keep_en	No	No		No		OUTPUT
mio_attr_o[10].schmitt_en	No	No		No		OUTPUT
mio_attr_o[10].od_en	No	No		No		OUTPUT
mio_attr_o[10].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[10].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[10].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[11].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[11].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[11].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[11].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[11].keep_en	No	No		No		OUTPUT
mio_attr_o[11].schmitt_en	No	No		No		OUTPUT
mio_attr_o[11].od_en	No	No		No		OUTPUT
mio_attr_o[11].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[11].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[11].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[12].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[12].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[12].pull_en	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
mio_attr_o[12].pull_select	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
mio_attr_o[12].keep_en	No	No		No		OUTPUT
mio_attr_o[12].schmitt_en	No	No		No		OUTPUT
mio_attr_o[12].od_en	No	No		No		OUTPUT
mio_attr_o[12].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[12].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[12].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[13].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[13].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[13].pull_en	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
mio_attr_o[13].pull_select	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
mio_attr_o[13].keep_en	No	No		No		OUTPUT
mio_attr_o[13].schmitt_en	No	No		No		OUTPUT
mio_attr_o[13].od_en	No	No		No		OUTPUT
mio_attr_o[13].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[13].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[13].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[14].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[14].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[14].pull_en	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
mio_attr_o[14].pull_select	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
mio_attr_o[14].keep_en	No	No		No		OUTPUT
mio_attr_o[14].schmitt_en	No	No		No		OUTPUT
mio_attr_o[14].od_en	No	No		No		OUTPUT
mio_attr_o[14].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[14].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[14].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[15].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[15].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[15].pull_en	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
mio_attr_o[15].pull_select	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
mio_attr_o[15].keep_en	No	No		No		OUTPUT
mio_attr_o[15].schmitt_en	No	No		No		OUTPUT
mio_attr_o[15].od_en	No	No		No		OUTPUT
mio_attr_o[15].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[15].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[15].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[16].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[16].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[16].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[16].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[16].keep_en	No	No		No		OUTPUT
mio_attr_o[16].schmitt_en	No	No		No		OUTPUT
mio_attr_o[16].od_en	No	No		No		OUTPUT
mio_attr_o[16].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[16].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[16].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[17].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[17].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[17].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[17].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[17].keep_en	No	No		No		OUTPUT
mio_attr_o[17].schmitt_en	No	No		No		OUTPUT
mio_attr_o[17].od_en	No	No		No		OUTPUT
mio_attr_o[17].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[17].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[17].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[18].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[18].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[18].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[18].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[18].keep_en	No	No		No		OUTPUT
mio_attr_o[18].schmitt_en	No	No		No		OUTPUT
mio_attr_o[18].od_en	No	No		No		OUTPUT
mio_attr_o[18].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[18].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[18].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[19].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[19].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[19].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[19].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[19].keep_en	No	No		No		OUTPUT
mio_attr_o[19].schmitt_en	No	No		No		OUTPUT
mio_attr_o[19].od_en	No	No		No		OUTPUT
mio_attr_o[19].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[19].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[19].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[20].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[20].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[20].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[20].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[20].keep_en	No	No		No		OUTPUT
mio_attr_o[20].schmitt_en	No	No		No		OUTPUT
mio_attr_o[20].od_en	No	No		No		OUTPUT
mio_attr_o[20].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[20].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[20].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[21].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[21].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[21].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[21].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[21].keep_en	No	No		No		OUTPUT
mio_attr_o[21].schmitt_en	No	No		No		OUTPUT
mio_attr_o[21].od_en	No	No		No		OUTPUT
mio_attr_o[21].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[21].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[21].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[22].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[22].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[22].pull_en	Yes	Yes	T36,T37,T38	Yes	T39,T40,T41	OUTPUT
mio_attr_o[22].pull_select	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	OUTPUT
mio_attr_o[22].keep_en	No	No		No		OUTPUT
mio_attr_o[22].schmitt_en	No	No		No		OUTPUT
mio_attr_o[22].od_en	No	No		No		OUTPUT
mio_attr_o[22].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[22].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[22].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[23].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[23].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[23].pull_en	Yes	Yes	T36,T37,T38	Yes	T39,T40,T41	OUTPUT
mio_attr_o[23].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[23].keep_en	No	No		No		OUTPUT
mio_attr_o[23].schmitt_en	No	No		No		OUTPUT
mio_attr_o[23].od_en	No	No		No		OUTPUT
mio_attr_o[23].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[23].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[23].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[24].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[24].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[24].pull_en	Yes	Yes	T36,T37,T38	Yes	T39,T40,T41	OUTPUT
mio_attr_o[24].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[24].keep_en	No	No		No		OUTPUT
mio_attr_o[24].schmitt_en	No	No		No		OUTPUT
mio_attr_o[24].od_en	No	No		No		OUTPUT
mio_attr_o[24].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[24].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[24].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[25].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[25].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[25].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].keep_en	No	No		No		OUTPUT
mio_attr_o[25].schmitt_en	No	No		No		OUTPUT
mio_attr_o[25].od_en	No	No		No		OUTPUT
mio_attr_o[25].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[25].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[25].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[26].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[26].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[26].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[26].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[26].keep_en	No	No		No		OUTPUT
mio_attr_o[26].schmitt_en	No	No		No		OUTPUT
mio_attr_o[26].od_en	No	No		No		OUTPUT
mio_attr_o[26].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[26].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[26].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[27].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[27].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[27].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[27].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[27].keep_en	No	No		No		OUTPUT
mio_attr_o[27].schmitt_en	No	No		No		OUTPUT
mio_attr_o[27].od_en	No	No		No		OUTPUT
mio_attr_o[27].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[27].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[27].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[28].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[28].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[28].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[28].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[28].keep_en	No	No		No		OUTPUT
mio_attr_o[28].schmitt_en	No	No		No		OUTPUT
mio_attr_o[28].od_en	No	No		No		OUTPUT
mio_attr_o[28].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[28].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[28].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[29].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[29].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[29].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[29].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[29].keep_en	No	No		No		OUTPUT
mio_attr_o[29].schmitt_en	No	No		No		OUTPUT
mio_attr_o[29].od_en	No	No		No		OUTPUT
mio_attr_o[29].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[29].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[29].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[30].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[30].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[30].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[30].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[30].keep_en	No	No		No		OUTPUT
mio_attr_o[30].schmitt_en	No	No		No		OUTPUT
mio_attr_o[30].od_en	No	No		No		OUTPUT
mio_attr_o[30].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[30].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[30].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[31].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[31].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[31].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[31].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[31].keep_en	No	No		No		OUTPUT
mio_attr_o[31].schmitt_en	No	No		No		OUTPUT
mio_attr_o[31].od_en	No	No		No		OUTPUT
mio_attr_o[31].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[31].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[31].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[32].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[32].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[32].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[32].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[32].keep_en	No	No		No		OUTPUT
mio_attr_o[32].schmitt_en	No	No		No		OUTPUT
mio_attr_o[32].od_en	No	No		No		OUTPUT
mio_attr_o[32].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[32].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[32].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[33].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[33].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[33].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[33].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[33].keep_en	No	No		No		OUTPUT
mio_attr_o[33].schmitt_en	No	No		No		OUTPUT
mio_attr_o[33].od_en	No	No		No		OUTPUT
mio_attr_o[33].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[33].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[33].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[34].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[34].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[34].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[34].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[34].keep_en	No	No		No		OUTPUT
mio_attr_o[34].schmitt_en	No	No		No		OUTPUT
mio_attr_o[34].od_en	No	No		No		OUTPUT
mio_attr_o[34].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[34].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[34].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[35].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[35].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[35].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[35].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[35].keep_en	No	No		No		OUTPUT
mio_attr_o[35].schmitt_en	No	No		No		OUTPUT
mio_attr_o[35].od_en	No	No		No		OUTPUT
mio_attr_o[35].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[35].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[35].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[36].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[36].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[36].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[36].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[36].keep_en	No	No		No		OUTPUT
mio_attr_o[36].schmitt_en	No	No		No		OUTPUT
mio_attr_o[36].od_en	No	No		No		OUTPUT
mio_attr_o[36].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[36].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[36].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[37].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[37].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[37].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[37].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[37].keep_en	No	No		No		OUTPUT
mio_attr_o[37].schmitt_en	No	No		No		OUTPUT
mio_attr_o[37].od_en	No	No		No		OUTPUT
mio_attr_o[37].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[37].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[37].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[38].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[38].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[38].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[38].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[38].keep_en	No	No		No		OUTPUT
mio_attr_o[38].schmitt_en	No	No		No		OUTPUT
mio_attr_o[38].od_en	No	No		No		OUTPUT
mio_attr_o[38].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[38].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[38].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[39].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[39].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[39].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[39].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[39].keep_en	No	No		No		OUTPUT
mio_attr_o[39].schmitt_en	No	No		No		OUTPUT
mio_attr_o[39].od_en	No	No		No		OUTPUT
mio_attr_o[39].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[39].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[39].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[40].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[40].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[40].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[40].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[40].keep_en	No	No		No		OUTPUT
mio_attr_o[40].schmitt_en	No	No		No		OUTPUT
mio_attr_o[40].od_en	No	No		No		OUTPUT
mio_attr_o[40].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[40].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[40].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[41].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[41].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[41].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[41].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[41].keep_en	No	No		No		OUTPUT
mio_attr_o[41].schmitt_en	No	No		No		OUTPUT
mio_attr_o[41].od_en	No	No		No		OUTPUT
mio_attr_o[41].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[41].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[41].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[42].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[42].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[42].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[42].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[42].keep_en	No	No		No		OUTPUT
mio_attr_o[42].schmitt_en	No	No		No		OUTPUT
mio_attr_o[42].od_en	No	No		No		OUTPUT
mio_attr_o[42].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[42].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[42].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[43].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[43].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[43].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[43].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[43].keep_en	No	No		No		OUTPUT
mio_attr_o[43].schmitt_en	No	No		No		OUTPUT
mio_attr_o[43].od_en	No	No		No		OUTPUT
mio_attr_o[43].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[43].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[43].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[44].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[44].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[44].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[44].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[44].keep_en	No	No		No		OUTPUT
mio_attr_o[44].schmitt_en	No	No		No		OUTPUT
mio_attr_o[44].od_en	No	No		No		OUTPUT
mio_attr_o[44].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[44].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[44].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[45].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[45].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[45].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[45].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[45].keep_en	No	No		No		OUTPUT
mio_attr_o[45].schmitt_en	No	No		No		OUTPUT
mio_attr_o[45].od_en	No	No		No		OUTPUT
mio_attr_o[45].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[45].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[45].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[46].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[46].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[46].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[46].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[46].keep_en	No	No		No		OUTPUT
mio_attr_o[46].schmitt_en	No	No		No		OUTPUT
mio_attr_o[46].od_en	No	No		No		OUTPUT
mio_attr_o[46].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[46].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
mio_attr_o[46].drive_strength[3:1]	No	No		No		OUTPUT
mio_out_o[46:0]	Yes	Yes	T14,T25,T26	Yes	T14,T7,T8	OUTPUT
mio_oe_o[46:0]	Yes	Yes	T25,T27,T28	Yes	T14,T7,T8	OUTPUT
mio_in_i[46:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
dio_attr_o[0].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[0].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[0].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[0].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[0].keep_en	No	No		No		OUTPUT
dio_attr_o[0].schmitt_en	No	No		No		OUTPUT
dio_attr_o[0].od_en	No	No		No		OUTPUT
dio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[0].drive_strength[0]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[0].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[1].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[1].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[1].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[1].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[1].keep_en	No	No		No		OUTPUT
dio_attr_o[1].schmitt_en	No	No		No		OUTPUT
dio_attr_o[1].od_en	No	No		No		OUTPUT
dio_attr_o[1].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[1].drive_strength[0]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[1].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[2].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[2].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[2].pull_en	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
dio_attr_o[2].pull_select	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
dio_attr_o[2].keep_en	No	No		No		OUTPUT
dio_attr_o[2].schmitt_en	No	No		No		OUTPUT
dio_attr_o[2].od_en	No	No		No		OUTPUT
dio_attr_o[2].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[2].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[2].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[3].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[3].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[3].pull_en	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
dio_attr_o[3].pull_select	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
dio_attr_o[3].keep_en	No	No		No		OUTPUT
dio_attr_o[3].schmitt_en	No	No		No		OUTPUT
dio_attr_o[3].od_en	No	No		No		OUTPUT
dio_attr_o[3].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[3].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[3].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[4].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[4].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[4].pull_en	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
dio_attr_o[4].pull_select	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
dio_attr_o[4].keep_en	No	No		No		OUTPUT
dio_attr_o[4].schmitt_en	No	No		No		OUTPUT
dio_attr_o[4].od_en	No	No		No		OUTPUT
dio_attr_o[4].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[4].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[4].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[5].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[5].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[5].pull_en	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
dio_attr_o[5].pull_select	Yes	Yes	T29,T30,T31	Yes	T10,T32,T11	OUTPUT
dio_attr_o[5].keep_en	No	No		No		OUTPUT
dio_attr_o[5].schmitt_en	No	No		No		OUTPUT
dio_attr_o[5].od_en	No	No		No		OUTPUT
dio_attr_o[5].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[5].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[5].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[6].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[6].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[6].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[6].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[6].keep_en	No	No		No		OUTPUT
dio_attr_o[6].schmitt_en	No	No		No		OUTPUT
dio_attr_o[6].od_en	No	No		No		OUTPUT
dio_attr_o[6].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[6].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[6].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[7].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[7].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[7].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[7].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[7].keep_en	No	No		No		OUTPUT
dio_attr_o[7].schmitt_en	No	No		No		OUTPUT
dio_attr_o[7].od_en	No	No		No		OUTPUT
dio_attr_o[7].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[7].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[7].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[8].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[8].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[8].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[8].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[8].keep_en	No	No		No		OUTPUT
dio_attr_o[8].schmitt_en	No	No		No		OUTPUT
dio_attr_o[8].od_en	No	No		No		OUTPUT
dio_attr_o[8].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[8].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[8].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[9].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[9].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[9].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[9].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[9].keep_en	No	No		No		OUTPUT
dio_attr_o[9].schmitt_en	No	No		No		OUTPUT
dio_attr_o[9].od_en	No	No		No		OUTPUT
dio_attr_o[9].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[9].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[9].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[10].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[10].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[10].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[10].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[10].keep_en	No	No		No		OUTPUT
dio_attr_o[10].schmitt_en	No	No		No		OUTPUT
dio_attr_o[10].od_en	No	No		No		OUTPUT
dio_attr_o[10].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[10].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[10].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[11].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[11].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[11].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[11].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[11].keep_en	No	No		No		OUTPUT
dio_attr_o[11].schmitt_en	No	No		No		OUTPUT
dio_attr_o[11].od_en	No	No		No		OUTPUT
dio_attr_o[11].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[11].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[11].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[12].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[12].virt_od_en	No	No		No		OUTPUT
dio_attr_o[12].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[12].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[12].keep_en	No	No		No		OUTPUT
dio_attr_o[12].schmitt_en	No	No		No		OUTPUT
dio_attr_o[12].od_en	No	No		No		OUTPUT
dio_attr_o[12].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[12].drive_strength[3:0]	No	No		No		OUTPUT
dio_attr_o[13].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[13].virt_od_en	No	No		No		OUTPUT
dio_attr_o[13].pull_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[13].pull_select	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[13].keep_en	No	No		No		OUTPUT
dio_attr_o[13].schmitt_en	No	No		No		OUTPUT
dio_attr_o[13].od_en	No	No		No		OUTPUT
dio_attr_o[13].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[13].drive_strength[3:0]	No	No		No		OUTPUT
dio_attr_o[14].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[14].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[14].pull_en	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
dio_attr_o[14].pull_select	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
dio_attr_o[14].keep_en	No	No		No		OUTPUT
dio_attr_o[14].schmitt_en	No	No		No		OUTPUT
dio_attr_o[14].od_en	No	No		No		OUTPUT
dio_attr_o[14].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[14].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[14].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[15].invert	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[15].virt_od_en	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[15].pull_en	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
dio_attr_o[15].pull_select	Yes	Yes	T29,T30,T31	Yes	T32,T11,T12	OUTPUT
dio_attr_o[15].keep_en	No	No		No		OUTPUT
dio_attr_o[15].schmitt_en	No	No		No		OUTPUT
dio_attr_o[15].od_en	No	No		No		OUTPUT
dio_attr_o[15].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[15].drive_strength[0]	Yes	Yes	T29,T30,*T31	Yes	T29,T30,T31	OUTPUT
dio_attr_o[15].drive_strength[3:1]	No	No		No		OUTPUT
dio_out_o[11:0]	Yes	Yes	T16,T17,*T18	Yes	T16,T17,T18	OUTPUT
dio_out_o[13:12]	No	No		No		OUTPUT
dio_out_o[15:14]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
dio_oe_o[15:0]	Yes	Yes	T22,T23,T24	Yes	T7,T8,T22	OUTPUT
dio_in_i[15:0]	Yes	Yes	T78,T22,T23	Yes	T22,T23,T24	INPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : pinmux

	Line No.	Total	Covered	Percent
Branches		776	569	73.32
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	1	25.00
TERNARY	481	4	1	25.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	3	75.00
TERNARY	481	4	3	75.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	464	2	2	100.00
TERNARY	468	2	2	100.00
TERNARY	477	4	2	50.00
TERNARY	481	4	2	50.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	2	50.00
TERNARY	517	4	2	50.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	3	75.00
TERNARY	517	4	3	75.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	2	50.00
TERNARY	517	4	2	50.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	3	75.00
TERNARY	517	4	3	75.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	2	50.00
TERNARY	517	4	2	50.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	3	75.00
TERNARY	517	4	3	75.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	3	75.00
TERNARY	517	4	3	75.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	3	75.00
TERNARY	517	4	3	75.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	3	75.00
TERNARY	517	4	3	75.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	2	50.00
TERNARY	517	4	2	50.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	2	50.00
TERNARY	517	4	2	50.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	2	50.00
TERNARY	517	4	2	50.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	1	25.00
TERNARY	517	4	1	25.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	1	25.00
TERNARY	517	4	1	25.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	2	50.00
TERNARY	517	4	2	50.00
TERNARY	500	2	2	100.00
TERNARY	504	2	2	100.00
TERNARY	513	4	2	50.00
TERNARY	517	4	2	50.00
TERNARY	546	2	1	50.00
TERNARY	546	2	1	50.00
TERNARY	546	2	1	50.00
TERNARY	546	2	1	50.00
TERNARY	546	2	2	100.00
TERNARY	546	2	1	50.00
TERNARY	546	2	1	50.00
TERNARY	546	2	1	50.00
IF	156	2	2	100.00
IF	408	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[0].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[0].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T14,T46
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T14,T46
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[1].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[1].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9,T46
0	1	-	Covered	T14,T7,T46
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9,T46
0	1	-	Covered	T14,T7,T46
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[2].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[2].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T14,T46
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T9
0	1	-	Covered	T14,T46
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[3].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[3].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T46,T47
0	1	-	Covered	T14,T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T46,T47
0	1	-	Covered	T14,T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[4].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[4].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T14,T46,T47
0	1	-	Covered	T9,T46
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T14,T46,T47
0	1	-	Covered	T9,T46
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[5].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[5].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T14,T9,T46
0	1	-	Covered	T7,T8,T46
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T14,T9,T46
0	1	-	Covered	T7,T8,T46
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[6].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[6].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T46
0	1	-	Covered	T14,T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T46
0	1	-	Covered	T14,T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[7].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[7].q) ?

Branches:

-1-	Status	Tests
1	Covered	T14,T7,T8
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T46,T47
0	1	-	Covered	T14,T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T46,T47
0	1	-	Covered	T14,T7,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[8].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[8].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[9].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[9].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[10].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[10].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[11].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[11].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[12].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[12].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[13].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[13].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[14].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[14].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[15].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[15].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[16].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[16].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[17].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[17].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[18].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[18].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[19].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[19].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[20].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[20].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[21].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[21].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[22].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[22].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[23].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[23].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[24].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[24].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[25].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[25].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[26].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[26].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[27].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[27].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[28].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[28].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[29].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[29].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[30].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[30].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[31].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[31].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[32].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[32].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[33].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[33].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[34].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[34].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[35].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[35].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[36].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[36].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[37].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[37].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[38].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[38].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[39].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[39].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[40].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[40].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[41].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[41].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[42].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[42].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[43].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[43].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[44].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[44].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[45].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[45].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	464	(reg2hw.mio_pad_sleep_status[46].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	468	(reg2hw.mio_pad_sleep_status[46].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	477	((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? 
-2-:	477	((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? 
-3-:	477	((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	481	((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? 
-2-:	481	((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? 
-3-:	481	((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[0].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[0].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[1].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[1].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[2].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[2].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[3].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[3].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[4].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[4].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[5].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[5].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[6].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[6].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T9
0	1	-	Covered	T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[7].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[7].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8,T9
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[8].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[8].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T8
0	1	-	Covered	T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[9].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[9].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[10].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[10].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[11].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[11].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Covered	T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[12].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[12].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[13].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[13].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[14].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[14].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T9
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	500	(reg2hw.dio_pad_sleep_status[15].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	504	(reg2hw.dio_pad_sleep_status[15].q) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	513	((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	513	((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	513	((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	517	((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	517	((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	517	((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered



	LineNo.	Expression
-1-:	546	(reg2hw.wkup_detector[0].miodio.q) ?

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	546	(reg2hw.wkup_detector[1].miodio.q) ?

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	546	(reg2hw.wkup_detector[2].miodio.q) ?

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	546	(reg2hw.wkup_detector[3].miodio.q) ?

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	546	(reg2hw.wkup_detector[4].miodio.q) ?

Branches:

-1-	Status	Tests
1	Covered	T48,T49
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	546	(reg2hw.wkup_detector[5].miodio.q) ?

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	546	(reg2hw.wkup_detector[6].miodio.q) ?

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	546	(reg2hw.wkup_detector[7].miodio.q) ?

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	156	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	408	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : pinmux

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	23	92.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	23	92.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	105529823	104882084	0	0
AonWkupReqKnownO_A	1340344	1164908	0	0
DftJtagTckKnown_A	105529823	104882084	0	0
DftJtagTmsKnown_A	105529823	104882084	0	0
DftJtagTrstKnown_A	105529823	104882084	0	0
DftStrapsKnown_A	105529823	104882084	0	0
DioKnownO_A	105529823	104882084	0	0
DioOeKnownO_A	105529823	104882084	0	0
FpvSecCmBusIntegrity_A	105529823	0	0	0
FpvSecCmRegWeOnehotCheck_A	105529823	5	0	0
LcJtagTckKnown_A	105529823	104882084	0	0
LcJtagTmsKnown_A	105529823	104882084	0	0
LcJtagTrstKnown_A	105529823	104882084	0	0
MioKnownO_A	105529823	104882084	0	0
MioOeKnownO_A	105529823	104882084	0	0
PinmuxWkupStable_A	1340344	3481	0	0
PwrMgrStrapSampleOnce0_A	105529823	1623	0	0
PwrMgrStrapSampleOnce1_A	105529823	0	0	908
RvJtagTckKnown_A	105529823	104882084	0	0
RvJtagTmsKnown_A	105529823	104882084	0	0
RvJtagTrstKnown_A	105529823	104882084	0	0
TlAReadyKnownO_A	105529823	104882084	0	0
TlDValidKnownO_A	105529823	104882084	0	0
UsbWakeDetectActiveKnownO_A	1340344	1164908	0	0
UsbWkupReqKnownO_A	1340344	1164908	0	0

AlertsKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

AonWkupReqKnownO_A

Name	Attempts	Real Successes
Total	1340344	1164908
T1	1003	838
T2	1052	887
T3	891	727
T4	1677	1452
T10	578	417
T39	2245	2083
T55	1481	1316
T79	345	183
T80	953	790
T81	666	504

DftJtagTckKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

DftJtagTmsKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

DftJtagTrstKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

DftStrapsKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

DioKnownO_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

DioOeKnownO_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

FpvSecCmBusIntegrity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105529823	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes
Total	105529823	5
T82	65583	1
T83	0	1
T84	0	1
T85	0	1
T86	0	1
T87	61655	0
T88	433743	0
T89	19494	0
T90	45450	0
T91	269908	0
T92	19062	0
T93	107245	0
T94	48145	0
T95	272117	0

LcJtagTckKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

LcJtagTmsKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

LcJtagTrstKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

MioKnownO_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

MioOeKnownO_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

PinmuxWkupStable_A

Name	Attempts	Real Successes
Total	1340344	3481
T14	0	22
T16	3586	410
T17	0	558
T18	0	591
T45	0	21
T46	0	156
T48	0	20
T96	0	528
T97	0	25
T98	0	26
T99	1052	0
T100	856	0
T101	418	0
T102	4423	0
T103	521	0
T104	715	0
T105	431	0
T106	362	0
T107	523	0

PwrMgrStrapSampleOnce0_A

Name	Attempts	Real Successes
Total	105529823	1623
T1	67517	2
T2	67467	2
T3	73746	2
T4	66763	2
T10	49292	1
T39	245863	1
T55	77332	2
T79	24697	1
T80	62627	2
T81	57851	1

PwrMgrStrapSampleOnce1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105529823	0	0	908

RvJtagTckKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

RvJtagTmsKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

RvJtagTrstKnown_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

TlAReadyKnownO_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

TlDValidKnownO_A

Name	Attempts	Real Successes
Total	105529823	104882084
T1	67517	67081
T2	67467	67054
T3	73746	73150
T4	66763	65927
T10	49292	48616
T39	245863	245269
T55	77332	76945
T79	24697	23618
T80	62627	62166
T81	57851	57176

UsbWakeDetectActiveKnownO_A

Name	Attempts	Real Successes
Total	1340344	1164908
T1	1003	838
T2	1052	887
T3	891	727
T4	1677	1452
T10	578	417
T39	2245	2083
T55	1481	1316
T79	345	183
T80	953	790
T81	666	504

UsbWkupReqKnownO_A

Name	Attempts	Real Successes
Total	1340344	1164908
T1	1003	838
T2	1052	887
T3	891	727
T4	1677	1452
T10	578	417
T39	2245	2083
T55	1481	1316
T79	345	183
T80	953	790
T81	666	504

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.38	77.07	79.39	65.10		73.32	92.00

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon	88.45	98.77	79.39	98.76		73.32	92.00