Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419644715	44933134	0	0
DepthKnown_A	419644715	419543522	0	0
RvalidKnown_A	419644715	419543522	0	0
WreadyKnown_A	419644715	419543522	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	44933134	0	0
T1	276430	35769	0	0
T2	276306	35404	0	0
T3	301714	32128	0	0
T4	265538	8778	0	0
T10	201017	26410	0	0
T39	102034	120385	0	0
T55	305221	33259	0	0
T79	96872	11594	0	0
T80	255935	32601	0	0
T81	236682	24253	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419644715	34584430	0	0
DepthKnown_A	419644715	419543522	0	0
RvalidKnown_A	419644715	419543522	0	0
WreadyKnown_A	419644715	419543522	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	34584430	0	0
T1	276430	26294	0	0
T2	276306	26056	0	0
T3	301714	24723	0	0
T4	265538	6838	0	0
T10	201017	16755	0	0
T39	102034	102170	0	0
T55	305221	25595	0	0
T79	96872	9197	0	0
T80	255935	23256	0	0
T81	236682	19848	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419644715	33795290	0	0
DepthKnown_A	419644715	419543522	0	0
RvalidKnown_A	419644715	419543522	0	0
WreadyKnown_A	419644715	419543522	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	33795290	0	0
T1	276430	19251	0	0
T2	276306	19183	0	0
T3	301714	22037	0	0
T4	265538	5282	0	0
T10	201017	11379	0	0
T39	102034	181798	0	0
T55	305221	18045	0	0
T79	96872	6697	0	0
T80	255935	17157	0	0
T81	236682	20875	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419644715	28490136	0	0
DepthKnown_A	419644715	419543522	0	0
RvalidKnown_A	419644715	419543522	0	0
WreadyKnown_A	419644715	419543522	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	28490136	0	0
T1	276430	18867	0	0
T2	276306	18796	0	0
T3	301714	21428	0	0
T4	265538	5166	0	0
T10	201017	11082	0	0
T39	102034	98895	0	0
T55	305221	17593	0	0
T79	96872	6562	0	0
T80	255935	16770	0	0
T81	236682	20609	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	419543522	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500218583	95357	0	0
DepthKnown_A	500218583	500105888	0	0
RvalidKnown_A	500218583	500105888	0	0
WreadyKnown_A	500218583	500105888	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	95357	0	0
T1	276430	149	0	0
T2	276306	149	0	0
T3	301714	289	0	0
T4	265538	15	0	0
T10	201017	12	0	0
T39	102034	40	0	0
T55	305221	68	0	0
T79	96872	13	0	0
T80	255935	149	0	0
T81	236682	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500218583	96888	0	0
DepthKnown_A	500218583	500105888	0	0
RvalidKnown_A	500218583	500105888	0	0
WreadyKnown_A	500218583	500105888	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	96888	0	0
T1	276430	149	0	0
T2	276306	149	0	0
T3	301714	289	0	0
T4	265538	15	0	0
T10	201017	12	0	0
T39	102034	40	0	0
T55	305221	68	0	0
T79	96872	13	0	0
T80	255935	149	0	0
T81	236682	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500218583	49626	0	0
DepthKnown_A	500218583	500105888	0	0
RvalidKnown_A	500218583	500105888	0	0
WreadyKnown_A	500218583	500105888	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	49626	0	0
T1	276430	95	0	0
T2	276306	95	0	0
T3	301714	171	0	0
T4	265538	14	0	0
T10	201017	11	0	0
T39	102034	5	0	0
T55	305221	63	0	0
T79	96872	12	0	0
T80	255935	95	0	0
T81	236682	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500218583	49626	0	0
DepthKnown_A	500218583	500105888	0	0
RvalidKnown_A	500218583	500105888	0	0
WreadyKnown_A	500218583	500105888	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	49626	0	0
T1	276430	95	0	0
T2	276306	95	0	0
T3	301714	171	0	0
T4	265538	14	0	0
T10	201017	11	0	0
T39	102034	5	0	0
T55	305221	63	0	0
T79	96872	12	0	0
T80	255935	95	0	0
T81	236682	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500218583	45731	0	0
DepthKnown_A	500218583	500105888	0	0
RvalidKnown_A	500218583	500105888	0	0
WreadyKnown_A	500218583	500105888	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	45731	0	0
T1	276430	54	0	0
T2	276306	54	0	0
T3	301714	118	0	0
T4	265538	1	0	0
T10	201017	1	0	0
T39	102034	35	0	0
T55	305221	5	0	0
T79	96872	1	0	0
T80	255935	54	0	0
T81	236682	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	500218583	47262	0	0
DepthKnown_A	500218583	500105888	0	0
RvalidKnown_A	500218583	500105888	0	0
WreadyKnown_A	500218583	500105888	0	0
gen_passthru_fifo.paramCheckPass	2847	2847	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	47262	0	0
T1	276430	54	0	0
T2	276306	54	0	0
T3	301714	118	0	0
T4	265538	1	0	0
T10	201017	1	0	0
T39	102034	35	0	0
T55	305221	5	0	0
T79	96872	1	0	0
T80	255935	54	0	0
T81	236682	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500218583	500105888	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2847	2847	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0