Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T79,T40	Yes	T39,T79,T40	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T39,T79,T40	Yes	T39,T79,T40	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T63,*T72	Yes	T5,T63,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T73,T74	Yes	T5,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T39,T79,T40	Yes	T39,T79,T40	INPUT
tl_o.a_ready	Yes	Yes	T39,T79,T40	Yes	T39,T79,T40	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T154,T36,T171	Yes	T154,T36,T171	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T79,T154,T36	Yes	T39,T79,T40	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T79,T154,T36	Yes	T39,T79,T40	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T206,*T69,*T70	Yes	T206,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T79,*T154,*T36	Yes	T79,T154,T36	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T39,T79,T40	Yes	T39,T79,T40	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T479,T671,T672	Yes	T479,T671,T672	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T479,T671,T672	Yes	T479,T671,T672	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T154,T36,T171	Yes	T154,T36,T171	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T154,T171,T179	Yes	T154,T171,T179	OUTPUT
intr_rx_watermark_o	Yes	Yes	T154,T171,T179	Yes	T154,T171,T179	OUTPUT
intr_tx_empty_o	Yes	Yes	T79,T154,T171	Yes	T79,T154,T171	OUTPUT
intr_rx_overflow_o	Yes	Yes	T79,T154,T171	Yes	T79,T154,T171	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_break_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_timeout_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T79,T40	Yes	T39,T79,T40	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T39,T79,T40	Yes	T39,T79,T40	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T63,*T72	Yes	T5,T63,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T73,T74	Yes	T5,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T39,T79,T40	Yes	T39,T79,T40	INPUT
tl_o.a_ready	Yes	Yes	T39,T79,T40	Yes	T39,T79,T40	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T154,T36,T171	Yes	T154,T36,T171	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T79,T154,T36	Yes	T39,T79,T40	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T79,T154,T36	Yes	T39,T79,T40	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T206,*T69,*T70	Yes	T206,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T79,*T154,*T36	Yes	T79,T154,T36	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T39,T79,T40	Yes	T39,T79,T40	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T479,T671,T123	Yes	T479,T671,T123	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T479,T671,T123	Yes	T479,T671,T123	OUTPUT
cio_rx_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T154,T36,T171	Yes	T154,T36,T171	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T154,T171,T155	Yes	T154,T171,T155	OUTPUT
intr_rx_watermark_o	Yes	Yes	T154,T171,T155	Yes	T154,T171,T155	OUTPUT
intr_tx_empty_o	Yes	Yes	T79,T154,T171	Yes	T79,T154,T171	OUTPUT
intr_rx_overflow_o	Yes	Yes	T79,T154,T171	Yes	T79,T154,T171	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_break_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_timeout_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T63,*T72	Yes	T5,T63,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T73,T74	Yes	T5,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T123,T190,T191	Yes	T123,T190,T191	INPUT
tl_o.a_ready	Yes	Yes	T123,T190,T191	Yes	T123,T190,T191	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T123,T190,T191	Yes	T123,T190,T191	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T123,T190,T191	Yes	T123,T190,T191	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T206,*T69,*T70	Yes	T206,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T190,*T191,*T192	Yes	T190,T191,T192	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T123,T190,T191	Yes	T123,T190,T191	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T123,T75,T76	Yes	T123,T75,T76	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T123,T75,T76	Yes	T123,T75,T76	OUTPUT
cio_rx_i	Yes	Yes	T32,T190,T191	Yes	T32,T11,T190	INPUT
cio_tx_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_watermark_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_tx_empty_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_overflow_o	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_break_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_timeout_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T179,T180,T279	Yes	T179,T180,T279	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T179,T180,T279	Yes	T179,T180,T279	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T63,*T72	Yes	T5,T63,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T73,T74	Yes	T5,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T179,T180,T123	Yes	T179,T180,T123	INPUT
tl_o.a_ready	Yes	Yes	T179,T180,T123	Yes	T179,T180,T123	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T111	Yes	T69,T70,T111	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T179,T180,T279	Yes	T179,T180,T279	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T179,T180,T123	Yes	T179,T180,T123	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T179,T180,T123	Yes	T179,T180,T123	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T206,*T69,*T70	Yes	T206,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T179,*T180,*T279	Yes	T179,T180,T279	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T179,T180,T123	Yes	T179,T180,T123	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T672,T123,T75	Yes	T672,T123,T75	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T672,T123,T75	Yes	T672,T123,T75	OUTPUT
cio_rx_i	Yes	Yes	T179,T180,T279	Yes	T179,T180,T279	INPUT
cio_tx_o	Yes	Yes	T179,T180,T279	Yes	T179,T180,T279	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T179,T180,T279	Yes	T179,T180,T279	OUTPUT
intr_rx_watermark_o	Yes	Yes	T179,T180,T279	Yes	T179,T180,T279	OUTPUT
intr_tx_empty_o	Yes	Yes	T179,T180,T279	Yes	T179,T180,T279	OUTPUT
intr_rx_overflow_o	Yes	Yes	T179,T180,T279	Yes	T179,T180,T279	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_break_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_timeout_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T13,T15,T286	Yes	T13,T15,T286	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T13,T15,T286	Yes	T13,T15,T286	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T5,*T63,*T72	Yes	T5,T63,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T73,T74	Yes	T5,T73,T74	INPUT
tl_i.a_valid	Yes	Yes	T13,T123,T15	Yes	T13,T123,T15	INPUT
tl_o.a_ready	Yes	Yes	T13,T123,T15	Yes	T13,T123,T15	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T15,T286	Yes	T13,T15,T286	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T13,T123,T15	Yes	T13,T123,T15	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T13,T123,T15	Yes	T13,T123,T15	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T206,*T69,*T70	Yes	T206,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T13,*T15,*T286	Yes	T13,T15,T286	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T13,T123,T15	Yes	T13,T123,T15	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T123,T75,T673	Yes	T123,T75,T673	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T123,T75,T673	Yes	T123,T75,T673	OUTPUT
cio_rx_i	Yes	Yes	T13,T15,T286	Yes	T13,T15,T286	INPUT
cio_tx_o	Yes	Yes	T13,T15,T286	Yes	T13,T15,T286	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T13,T15,T286	Yes	T13,T15,T286	OUTPUT
intr_rx_watermark_o	Yes	Yes	T13,T15,T286	Yes	T13,T15,T286	OUTPUT
intr_tx_empty_o	Yes	Yes	T13,T15,T286	Yes	T13,T15,T286	OUTPUT
intr_rx_overflow_o	Yes	Yes	T13,T15,T286	Yes	T13,T15,T286	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_break_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_timeout_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T283,T87,T284	Yes	T283,T87,T284	OUTPUT

*Tests covering at least one bit in the range