Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.01	94.12	89.29	100.00		100.00	66.67	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	839289430	3816	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	839289430	3816	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	3816	0	0
T1	276430	4	0	0
T2	276306	4	0	0
T3	301714	4	0	0
T4	265538	1	0	0
T10	201017	1	0	0
T39	102034	18	0	0
T55	305221	4	0	0
T79	96872	1	0	0
T80	255935	4	0	0
T81	236682	2	0	0
T123	784354	0	0	0
T144	105084	11	0	0
T145	0	4	0	0
T146	0	4	0	0
T152	138849	0	0	0
T155	231051	0	0	0
T254	627531	0	0	0
T273	0	4	0	0
T274	0	8	0	0
T275	0	11	0	0
T276	141586	0	0	0
T277	160584	0	0	0
T278	222054	0	0	0
T279	213274	0	0	0
T280	997151	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	3816	0	0
T1	276430	4	0	0
T2	276306	4	0	0
T3	301714	4	0	0
T4	265538	1	0	0
T10	201017	1	0	0
T39	102034	18	0	0
T55	305221	4	0	0
T79	96872	1	0	0
T80	255935	4	0	0
T81	236682	2	0	0
T123	784354	0	0	0
T144	105084	11	0	0
T145	0	4	0	0
T146	0	4	0	0
T152	138849	0	0	0
T155	231051	0	0	0
T254	627531	0	0	0
T273	0	4	0	0
T274	0	8	0	0
T275	0	11	0	0
T276	141586	0	0	0
T277	160584	0	0	0
T278	222054	0	0	0
T279	213274	0	0	0
T280	997151	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	419644715	42	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	419644715	42	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	42	0	0
T123	784354	0	0	0
T144	105084	11	0	0
T145	0	4	0	0
T146	0	4	0	0
T152	138849	0	0	0
T155	231051	0	0	0
T254	627531	0	0	0
T273	0	4	0	0
T274	0	8	0	0
T275	0	11	0	0
T276	141586	0	0	0
T277	160584	0	0	0
T278	222054	0	0	0
T279	213274	0	0	0
T280	997151	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	42	0	0
T123	784354	0	0	0
T144	105084	11	0	0
T145	0	4	0	0
T146	0	4	0	0
T152	138849	0	0	0
T155	231051	0	0	0
T254	627531	0	0	0
T273	0	4	0	0
T274	0	8	0	0
T275	0	11	0	0
T276	141586	0	0	0
T277	160584	0	0	0
T278	222054	0	0	0
T279	213274	0	0	0
T280	997151	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	419644715	3774	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	419644715	3774	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	3774	0	0
T1	276430	4	0	0
T2	276306	4	0	0
T3	301714	4	0	0
T4	265538	1	0	0
T10	201017	1	0	0
T39	102034	18	0	0
T55	305221	4	0	0
T79	96872	1	0	0
T80	255935	4	0	0
T81	236682	2	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	3774	0	0
T1	276430	4	0	0
T2	276306	4	0	0
T3	301714	4	0	0
T4	265538	1	0	0
T10	201017	1	0	0
T39	102034	18	0	0
T55	305221	4	0	0
T79	96872	1	0	0
T80	255935	4	0	0
T81	236682	2	0	0