Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T145,T146,T273
0	1	Covered	T145,T146,T273
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T146,T273
1	Covered	T145,T146,T273

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T146,T273
1	Covered	T145,T146,T273

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T145,T146,T273
1	1	Covered	T145,T146,T273

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T146,T273
1	0	Covered	T145,T146,T273
1	1	Covered	T145,T146,T273

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T145,T146,T273

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T146,T273
0	Covered	T145,T146,T273

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T146,T273
0	Covered	T145,T146,T273

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	839289430	822248448	0	0
CheckNGreaterZero_A	1912	1912	0	0
GntImpliesReady_A	839289430	5428	0	0
GntImpliesValid_A	839289430	5428	0	0
GrantKnown_A	839289430	822248448	0	0
IdxKnown_A	839289430	822248448	0	0
IndexIsCorrect_A	839289430	5428	0	0
NoReadyValidNoGrant_A	839289430	0	0	0
Priority_A	839289430	5428	0	0
ReadyAndValidImplyGrant_A	839289430	5428	0	0
ReqAndReadyImplyGrant_A	839289430	5428	0	0
ReqImpliesValid_A	839289430	5428	0	0
ValidKnown_A	839289430	822248448	0	0
gen_data_port_assertion.DataFlow_A	839289430	5428	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	822248448	0	0
T1	552860	552620	0	0
T2	552612	552386	0	0
T3	603428	603180	0	0
T4	531076	530836	0	0
T10	402034	401932	0	0
T39	204068	204058	0	0
T55	610442	610108	0	0
T79	193744	193634	0	0
T80	511870	511650	0	0
T81	473364	473262	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1912	1912	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T10	2	2	0	0
T39	2	2	0	0
T55	2	2	0	0
T79	2	2	0	0
T80	2	2	0	0
T81	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	5428	0	0
T11	156584	0	0	0
T33	258492	0	0	0
T145	148118	1817	0	0
T146	0	1803	0	0
T160	433504	0	0	0
T215	1776070	0	0	0
T222	702516	0	0	0
T273	0	1808	0	0
T310	560322	0	0	0
T328	316594	0	0	0
T340	1335074	0	0	0
T341	1378612	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	5428	0	0
T11	156584	0	0	0
T33	258492	0	0	0
T145	148118	1817	0	0
T146	0	1803	0	0
T160	433504	0	0	0
T215	1776070	0	0	0
T222	702516	0	0	0
T273	0	1808	0	0
T310	560322	0	0	0
T328	316594	0	0	0
T340	1335074	0	0	0
T341	1378612	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	822248448	0	0
T1	552860	552620	0	0
T2	552612	552386	0	0
T3	603428	603180	0	0
T4	531076	530836	0	0
T10	402034	401932	0	0
T39	204068	204058	0	0
T55	610442	610108	0	0
T79	193744	193634	0	0
T80	511870	511650	0	0
T81	473364	473262	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	822248448	0	0
T1	552860	552620	0	0
T2	552612	552386	0	0
T3	603428	603180	0	0
T4	531076	530836	0	0
T10	402034	401932	0	0
T39	204068	204058	0	0
T55	610442	610108	0	0
T79	193744	193634	0	0
T80	511870	511650	0	0
T81	473364	473262	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	5428	0	0
T11	156584	0	0	0
T33	258492	0	0	0
T145	148118	1817	0	0
T146	0	1803	0	0
T160	433504	0	0	0
T215	1776070	0	0	0
T222	702516	0	0	0
T273	0	1808	0	0
T310	560322	0	0	0
T328	316594	0	0	0
T340	1335074	0	0	0
T341	1378612	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	5428	0	0
T11	156584	0	0	0
T33	258492	0	0	0
T145	148118	1817	0	0
T146	0	1803	0	0
T160	433504	0	0	0
T215	1776070	0	0	0
T222	702516	0	0	0
T273	0	1808	0	0
T310	560322	0	0	0
T328	316594	0	0	0
T340	1335074	0	0	0
T341	1378612	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	5428	0	0
T11	156584	0	0	0
T33	258492	0	0	0
T145	148118	1817	0	0
T146	0	1803	0	0
T160	433504	0	0	0
T215	1776070	0	0	0
T222	702516	0	0	0
T273	0	1808	0	0
T310	560322	0	0	0
T328	316594	0	0	0
T340	1335074	0	0	0
T341	1378612	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	5428	0	0
T11	156584	0	0	0
T33	258492	0	0	0
T145	148118	1817	0	0
T146	0	1803	0	0
T160	433504	0	0	0
T215	1776070	0	0	0
T222	702516	0	0	0
T273	0	1808	0	0
T310	560322	0	0	0
T328	316594	0	0	0
T340	1335074	0	0	0
T341	1378612	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	5428	0	0
T11	156584	0	0	0
T33	258492	0	0	0
T145	148118	1817	0	0
T146	0	1803	0	0
T160	433504	0	0	0
T215	1776070	0	0	0
T222	702516	0	0	0
T273	0	1808	0	0
T310	560322	0	0	0
T328	316594	0	0	0
T340	1335074	0	0	0
T341	1378612	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	822248448	0	0
T1	552860	552620	0	0
T2	552612	552386	0	0
T3	603428	603180	0	0
T4	531076	530836	0	0
T10	402034	401932	0	0
T39	204068	204058	0	0
T55	610442	610108	0	0
T79	193744	193634	0	0
T80	511870	511650	0	0
T81	473364	473262	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839289430	5428	0	0
T11	156584	0	0	0
T33	258492	0	0	0
T145	148118	1817	0	0
T146	0	1803	0	0
T160	433504	0	0	0
T215	1776070	0	0	0
T222	702516	0	0	0
T273	0	1808	0	0
T310	560322	0	0	0
T328	316594	0	0	0
T340	1335074	0	0	0
T341	1378612	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T145,T146,T273
0	1	Covered	T145,T146,T273
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T146,T273
1	Covered	T145,T146,T273

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T146,T273
1	Covered	T145,T146,T273

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T145,T146,T273
1	1	Covered	T145,T146,T273

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T146,T273
1	0	Covered	T145,T146,T273
1	1	Covered	T145,T146,T273

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T145,T146,T273

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T146,T273
0	Covered	T145,T146,T273

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T146,T273
0	Covered	T145,T146,T273

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419644715	411124224	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	419644715	4396	0	0
GntImpliesValid_A	419644715	4396	0	0
GrantKnown_A	419644715	411124224	0	0
IdxKnown_A	419644715	411124224	0	0
IndexIsCorrect_A	419644715	4396	0	0
NoReadyValidNoGrant_A	419644715	0	0	0
Priority_A	419644715	4396	0	0
ReadyAndValidImplyGrant_A	419644715	4396	0	0
ReqAndReadyImplyGrant_A	419644715	4396	0	0
ReqImpliesValid_A	419644715	4396	0	0
ValidKnown_A	419644715	411124224	0	0
gen_data_port_assertion.DataFlow_A	419644715	4396	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	411124224	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	4396	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	1473	0	0
T146	0	1459	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	1464	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	4396	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	1473	0	0
T146	0	1459	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	1464	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	411124224	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	411124224	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	4396	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	1473	0	0
T146	0	1459	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	1464	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	4396	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	1473	0	0
T146	0	1459	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	1464	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	4396	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	1473	0	0
T146	0	1459	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	1464	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	4396	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	1473	0	0
T146	0	1459	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	1464	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	4396	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	1473	0	0
T146	0	1459	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	1464	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	411124224	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	4396	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	1473	0	0
T146	0	1459	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	1464	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T145,T146,T273
0	1	Covered	T145,T146,T273
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T146,T273
1	Covered	T145,T146,T273

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T145,T146,T273
1	Covered	T145,T146,T273

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T145,T146,T273
1	1	Covered	T145,T146,T273

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T145,T146,T273
1	0	Covered	T145,T146,T273
1	1	Covered	T145,T146,T273

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T145,T146,T273

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T146,T273
0	Covered	T145,T146,T273

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T145,T146,T273
0	Covered	T145,T146,T273

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419644715	411124224	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	419644715	1032	0	0
GntImpliesValid_A	419644715	1032	0	0
GrantKnown_A	419644715	411124224	0	0
IdxKnown_A	419644715	411124224	0	0
IndexIsCorrect_A	419644715	1032	0	0
NoReadyValidNoGrant_A	419644715	0	0	0
Priority_A	419644715	1032	0	0
ReadyAndValidImplyGrant_A	419644715	1032	0	0
ReqAndReadyImplyGrant_A	419644715	1032	0	0
ReqImpliesValid_A	419644715	1032	0	0
ValidKnown_A	419644715	411124224	0	0
gen_data_port_assertion.DataFlow_A	419644715	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	411124224	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T39	1	1	0	0
T55	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	1032	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	344	0	0
T146	0	344	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	344	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	1032	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	344	0	0
T146	0	344	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	344	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	411124224	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	411124224	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	1032	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	344	0	0
T146	0	344	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	344	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	1032	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	344	0	0
T146	0	344	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	344	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	1032	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	344	0	0
T146	0	344	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	344	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	1032	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	344	0	0
T146	0	344	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	344	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	1032	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	344	0	0
T146	0	344	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	344	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	411124224	0	0
T1	276430	276310	0	0
T2	276306	276193	0	0
T3	301714	301590	0	0
T4	265538	265418	0	0
T10	201017	200966	0	0
T39	102034	102029	0	0
T55	305221	305054	0	0
T79	96872	96817	0	0
T80	255935	255825	0	0
T81	236682	236631	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419644715	1032	0	0
T11	78292	0	0	0
T33	129246	0	0	0
T145	74059	344	0	0
T146	0	344	0	0
T160	216752	0	0	0
T215	888035	0	0	0
T222	351258	0	0	0
T273	0	344	0	0
T310	280161	0	0	0
T328	158297	0	0	0
T340	667537	0	0	0
T341	689306	0	0	0