Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2273128	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27189153

1

T1

6038

T2

4320

T3

33954

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19587538	1			T1	2347		T2	1423		T3	30205
values[0x0]	7986848	1			T1	3691		T2	2897		T3	3749
values[0x1]	1887895	1			T1	155		T2	219		T3	7712

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	535160	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28927121

1

T1

6193

T2

4539

T3

41666

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13698103	1			T1	3097		T2	2270		T3	20833
valid_sources[0x01]	13697283	1			T1	3096		T2	2269		T3	20833
valid_sources[0x02]	33729	1			T199	1		T483	481		T165	823
valid_sources[0x03]	33271	1			T199	1		T483	377		T165	775
valid_sources[0x04]	33037	1			T67	3		T176	14		T483	496
valid_sources[0x05]	33288	1			T67	1		T483	587		T165	836
valid_sources[0x06]	33194	1			T483	303		T165	830		T166	417
valid_sources[0x07]	32902	1			T483	537		T165	745		T166	398
valid_sources[0x08]	33246	1			T67	4		T199	2		T483	381
valid_sources[0x09]	33840	1			T67	3		T483	658		T165	754
valid_sources[0x0a]	33998	1			T357	2		T483	508		T165	831
valid_sources[0x0b]	33005	1			T67	2		T483	383		T165	809
valid_sources[0x0c]	33534	1			T176	3		T199	1		T483	475
valid_sources[0x0d]	33326	1			T67	1		T357	3		T483	381
valid_sources[0x0e]	33555	1			T20	39		T67	2		T357	3
valid_sources[0x0f]	33488	1			T199	1		T483	515		T165	785
valid_sources[0x10]	33083	1			T199	2		T483	530		T165	852
valid_sources[0x11]	33356	1			T199	2		T483	516		T165	774
valid_sources[0x12]	33710	1			T199	1		T483	438		T165	809
valid_sources[0x13]	32894	1			T357	1		T483	583		T165	872
valid_sources[0x14]	33488	1			T199	1		T483	484		T165	753
valid_sources[0x15]	33448	1			T67	2		T357	5		T483	432
valid_sources[0x16]	34246	1			T67	1		T483	380		T165	789
valid_sources[0x17]	33576	1			T67	2		T357	4		T483	353
valid_sources[0x18]	33775	1			T199	1		T483	603		T165	792
valid_sources[0x19]	32515	1			T483	315		T165	807		T166	377
valid_sources[0x1a]	33715	1			T483	537		T165	729		T166	398
valid_sources[0x1b]	32960	1			T199	1		T483	356		T165	801
valid_sources[0x1c]	33767	1			T483	620		T165	764		T166	352
valid_sources[0x1d]	34202	1			T357	1		T483	616		T165	772
valid_sources[0x1e]	33234	1			T483	386		T165	779		T166	362
valid_sources[0x1f]	32853	1			T67	1		T199	1		T483	489
valid_sources[0x20]	32902	1			T483	693		T165	731		T166	388

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19002658

1

T1

2347

T2

1423

T3

30205

values[0x0]

all_enables

biggest_size

7946293

1

T1

3691

T2

2897

T3

3749

values[0x1]

all_enables

biggest_size

240202

1

T20

16

T66

21

T67

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2960015	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

467295

1

T72

265

T73

411

T74

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1159598	1			T72	583		T73	931		T74	70
values[0x0]	1106304	1			T72	620		T73	951		T74	56
values[0x1]	1161408	1			T72	626		T73	950		T74	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2291542	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1135768

1

T72

609

T73

947

T74

65

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53390	1			T72	4		T73	45		T74	1
valid_sources[0x01]	53702	1			T72	24		T73	42		T74	7
valid_sources[0x02]	53503	1			T72	41		T73	48		T75	2
valid_sources[0x03]	53313	1			T72	25		T73	44		T75	3
valid_sources[0x04]	53530	1			T72	44		T73	50		T74	4
valid_sources[0x05]	53934	1			T72	34		T73	53		T74	5
valid_sources[0x06]	53852	1			T72	20		T73	42		T74	2
valid_sources[0x07]	52303	1			T72	19		T73	48		T74	3
valid_sources[0x08]	53015	1			T72	69		T73	44		T74	10
valid_sources[0x09]	54217	1			T72	19		T73	36		T74	4
valid_sources[0x0a]	54055	1			T72	27		T73	51		T74	5
valid_sources[0x0b]	54715	1			T72	44		T73	40		T74	1
valid_sources[0x0c]	53860	1			T72	56		T73	44		T74	6
valid_sources[0x0d]	53048	1			T72	22		T73	48		T74	6
valid_sources[0x0e]	55060	1			T72	28		T73	44		T74	1
valid_sources[0x0f]	54043	1			T72	49		T73	45		T75	8
valid_sources[0x10]	54699	1			T72	24		T73	52		T74	2
valid_sources[0x11]	54184	1			T72	15		T73	43		T74	1
valid_sources[0x12]	55048	1			T72	41		T73	48		T74	6
valid_sources[0x13]	53613	1			T72	18		T73	42		T74	2
valid_sources[0x14]	53530	1			T72	19		T73	39		T74	2
valid_sources[0x15]	53775	1			T72	24		T73	43		T74	2
valid_sources[0x16]	52487	1			T72	17		T73	46		T74	1
valid_sources[0x17]	53877	1			T72	22		T73	49		T74	5
valid_sources[0x18]	52619	1			T72	44		T73	37		T75	2
valid_sources[0x19]	53112	1			T72	18		T73	43		T74	4
valid_sources[0x1a]	54090	1			T72	29		T73	35		T74	4
valid_sources[0x1b]	53161	1			T72	9		T73	49		T75	1
valid_sources[0x1c]	53861	1			T72	35		T73	36		T105	43
valid_sources[0x1d]	53540	1			T72	34		T73	43		T74	5
valid_sources[0x1e]	53475	1			T72	38		T73	40		T74	2
valid_sources[0x1f]	53098	1			T72	23		T73	30		T74	2
valid_sources[0x20]	52928	1			T72	38		T73	48		T74	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49041

1

T72

36

T73

46

T74

6

values[0x0]

all_enables

biggest_size

369147

1

T72

202

T73

317

T74

21

values[0x1]

all_enables

biggest_size

49107

1

T72

27

T73

48

T74

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3149936	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

513471

1

T72

248

T73

358

T74

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1253537	1			T72	674		T73	893		T74	52
values[0x0]	1156095	1			T72	608		T73	869		T74	41
values[0x1]	1253775	1			T72	650		T73	919		T74	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2416133	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1247274

1

T72

642

T73

876

T74

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56699	1			T72	53		T73	31		T74	4
valid_sources[0x01]	56392	1			T72	19		T73	37		T74	6
valid_sources[0x02]	57474	1			T72	27		T73	44		T75	1
valid_sources[0x03]	57304	1			T72	36		T73	37		T75	2
valid_sources[0x04]	56818	1			T72	33		T73	52		T74	4
valid_sources[0x05]	56687	1			T72	9		T73	48		T74	1
valid_sources[0x06]	56801	1			T72	32		T73	61		T75	1
valid_sources[0x07]	57782	1			T72	24		T73	38		T75	2
valid_sources[0x08]	57137	1			T72	17		T73	46		T75	1
valid_sources[0x09]	56782	1			T72	45		T73	37		T74	1
valid_sources[0x0a]	57174	1			T72	17		T73	29		T74	5
valid_sources[0x0b]	57256	1			T72	19		T73	64		T75	2
valid_sources[0x0c]	57060	1			T72	18		T73	44		T75	3
valid_sources[0x0d]	56462	1			T72	29		T73	22		T74	10
valid_sources[0x0e]	57703	1			T72	61		T73	43		T74	1
valid_sources[0x0f]	57557	1			T72	18		T73	29		T74	1
valid_sources[0x10]	57616	1			T72	40		T73	34		T74	3
valid_sources[0x11]	57868	1			T72	12		T73	27		T75	2
valid_sources[0x12]	57274	1			T72	22		T73	34		T75	2
valid_sources[0x13]	57759	1			T72	27		T73	46		T105	34
valid_sources[0x14]	57362	1			T72	25		T73	47		T74	3
valid_sources[0x15]	57740	1			T72	62		T73	44		T74	2
valid_sources[0x16]	56568	1			T72	44		T73	43		T75	5
valid_sources[0x17]	58059	1			T72	20		T73	34		T74	2
valid_sources[0x18]	57190	1			T72	17		T73	34		T75	4
valid_sources[0x19]	56944	1			T72	22		T73	33		T74	1
valid_sources[0x1a]	58167	1			T72	30		T73	24		T74	3
valid_sources[0x1b]	57477	1			T72	36		T73	31		T74	1
valid_sources[0x1c]	57418	1			T72	23		T73	30		T74	2
valid_sources[0x1d]	57610	1			T72	51		T73	51		T75	2
valid_sources[0x1e]	57184	1			T72	29		T73	37		T74	6
valid_sources[0x1f]	56781	1			T72	12		T73	42		T74	11
valid_sources[0x20]	57249	1			T72	19		T73	48		T74	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54025

1

T72

32

T73

38

T74

3

values[0x0]

all_enables

biggest_size

405695

1

T72

197

T73

284

T74

19

values[0x1]

all_enables

biggest_size

53751

1

T72

19

T73

36

T74

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2986609	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

472514

1

T72

243

T73

355

T74

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1170462	1			T72	589		T73	972		T74	27
values[0x0]	1117987	1			T72	606		T73	867		T74	38
values[0x1]	1170674	1			T72	586		T73	854		T74	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2314090	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1145033

1

T72

585

T73

865

T74

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54846	1			T72	29		T73	41		T74	1
valid_sources[0x01]	54208	1			T72	36		T73	50		T74	1
valid_sources[0x02]	54893	1			T72	30		T73	52		T75	3
valid_sources[0x03]	53550	1			T72	11		T73	39		T74	2
valid_sources[0x04]	54064	1			T72	31		T73	35		T74	2
valid_sources[0x05]	53748	1			T72	23		T73	35		T74	2
valid_sources[0x06]	53631	1			T72	21		T73	39		T75	5
valid_sources[0x07]	54396	1			T72	36		T73	45		T74	1
valid_sources[0x08]	53950	1			T72	32		T73	41		T74	1
valid_sources[0x09]	53750	1			T72	33		T73	44		T74	1
valid_sources[0x0a]	53961	1			T72	33		T73	46		T74	3
valid_sources[0x0b]	54300	1			T72	22		T73	33		T75	2
valid_sources[0x0c]	54205	1			T72	29		T73	31		T75	4
valid_sources[0x0d]	54265	1			T72	26		T73	44		T74	1
valid_sources[0x0e]	54747	1			T72	19		T73	48		T74	2
valid_sources[0x0f]	54384	1			T72	38		T73	45		T74	2
valid_sources[0x10]	53964	1			T72	27		T73	46		T74	3
valid_sources[0x11]	54028	1			T72	36		T73	41		T74	3
valid_sources[0x12]	54872	1			T72	24		T73	40		T74	3
valid_sources[0x13]	54198	1			T72	39		T73	44		T74	4
valid_sources[0x14]	54007	1			T72	27		T73	49		T74	1
valid_sources[0x15]	55268	1			T72	33		T73	36		T74	1
valid_sources[0x16]	54443	1			T72	28		T73	46		T75	1
valid_sources[0x17]	54655	1			T72	20		T73	41		T74	4
valid_sources[0x18]	54262	1			T72	30		T73	37		T74	5
valid_sources[0x19]	54283	1			T72	21		T73	33		T74	1
valid_sources[0x1a]	54000	1			T72	21		T73	40		T74	2
valid_sources[0x1b]	52937	1			T72	20		T73	40		T74	2
valid_sources[0x1c]	53896	1			T72	14		T73	47		T75	2
valid_sources[0x1d]	54439	1			T72	27		T73	42		T105	30
valid_sources[0x1e]	53262	1			T72	33		T73	39		T74	1
valid_sources[0x1f]	54091	1			T72	27		T73	40		T74	1
valid_sources[0x20]	53205	1			T72	30		T73	40		T74	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49620

1

T72

16

T73

32

T74

1

values[0x0]

all_enables

biggest_size

373510

1

T72

208

T73

286

T74

11

values[0x1]

all_enables

biggest_size

49384

1

T72

19

T73

37

T74

3