Unified Coverage Report :: Module :: ibex_top

Module : ibex_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.53			94.53

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_core	96.88			96.88

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88			96.88

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88			96.88

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.44	96.47	89.29	100.00		100.00	71.43	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : ibex_top

	Total	Covered	Percent
Totals	40	34	85.00
Total Bits	822	777	94.53
Total Bits 0->1	411	389	94.65
Total Bits 1->0	411	388	94.40

Ports	40	34	85.00
Port Bits	822	777	94.53
Port Bits 0->1	411	389	94.65
Port Bits 1->0	411	388	94.40

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
instr_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[16:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
instr_addr_o[18:17]	No	No		No		OUTPUT
instr_addr_o[19]	No	No		Yes	T322,T323,T324	OUTPUT
instr_addr_o[27:20]	No	No		No		OUTPUT
instr_addr_o[29:28]	Yes	Yes	*T214,*T43,*T241	Yes	T214,T43,T241	OUTPUT
instr_addr_o[30]	No	No		No		OUTPUT
instr_addr_o[31]	Yes	Yes	T134,T135,T260	Yes	T134,T135,T260	OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_err_i	Yes	Yes	T61,T198,T134	Yes	T61,T198,T134	INPUT
data_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_we_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_be_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_intg_o[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_err_i	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
irq_software_i	Yes	Yes	T20,T138,T91	Yes	T20,T138,T91	INPUT
irq_timer_i	Yes	Yes	T224,T225,T109	Yes	T224,T225,T109	INPUT
irq_external_i	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	Yes	Yes	T61,T226,T62	Yes	T61,T226,T62	INPUT
scramble_key_valid_i	Yes	Yes	T134,T135,T136	Yes	T134,T135,T136	INPUT
scramble_key_i[127:0]	Yes	Yes	T1,T2,T3	Yes	T79,T6,T133	INPUT
scramble_nonce_i[63:0]	Yes	Yes	T34,T79,T6	Yes	T1,T3,T34	INPUT
scramble_req_o	Yes	Yes	T134,T135,T136	Yes	T134,T135,T136	OUTPUT
debug_req_i	Yes	Yes	T193,T194,T227	Yes	T193,T194,T227	INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T1,T34,T4	Yes	T1,T2,T3	INPUT
alert_minor_o	Yes	Yes	T325	Yes	T325,T326	OUTPUT
alert_major_internal_o	Yes	Yes	T327,T325,T326	Yes	T327,T325,T326	OUTPUT
alert_major_bus_o	Yes	Yes	T133,T132,T214	Yes	T133,T132,T214	OUTPUT
core_sleep_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

	Total	Covered	Percent
Totals	36	34	94.44
Total Bits	802	777	96.88
Total Bits 0->1	401	389	97.01
Total Bits 1->0	401	388	96.76

Ports	36	34	94.44
Port Bits	802	777	96.88
Port Bits 0->1	401	389	97.01
Port Bits 1->0	401	388	96.76

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
instr_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[16:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
instr_addr_o[18:17]	No	No		No		OUTPUT
instr_addr_o[19]	No	No		Yes	T322,T323,T324	OUTPUT
instr_addr_o[27:20]	No	No		No		OUTPUT
instr_addr_o[29:28]	Yes	Yes	*T214,*T43,*T241	Yes	T214,T43,T241	OUTPUT
instr_addr_o[30]	No	No		No		OUTPUT
instr_addr_o[31]	Yes	Yes	T134,T135,T260	Yes	T134,T135,T260	OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
instr_err_i	Yes	Yes	T61,T198,T134	Yes	T61,T198,T134	INPUT
data_req_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_gnt_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rvalid_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_we_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_be_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_wdata_intg_o[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
data_rdata_i[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_err_i	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	INPUT
irq_software_i	Yes	Yes	T20,T138,T91	Yes	T20,T138,T91	INPUT
irq_timer_i	Yes	Yes	T224,T225,T109	Yes	T224,T225,T109	INPUT
irq_external_i	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	Yes	Yes	T61,T226,T62	Yes	T61,T226,T62	INPUT
scramble_key_valid_i	Yes	Yes	T134,T135,T136	Yes	T134,T135,T136	INPUT
scramble_key_i[127:0]	Yes	Yes	T1,T2,T3	Yes	T79,T6,T133	INPUT
scramble_nonce_i[63:0]	Yes	Yes	T34,T79,T6	Yes	T1,T3,T34	INPUT
scramble_req_o	Yes	Yes	T134,T135,T136	Yes	T134,T135,T136	OUTPUT
debug_req_i	Yes	Yes	T193,T194,T227	Yes	T193,T194,T227	INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T1,T34,T4	Yes	T1,T2,T3	INPUT
alert_minor_o	Yes	Yes	T325	Yes	T325,T326	OUTPUT
alert_major_internal_o	Yes	Yes	T327,T325,T326	Yes	T327,T325,T326	OUTPUT
alert_major_bus_o	Yes	Yes	T133,T132,T214	Yes	T133,T132,T214	OUTPUT
core_sleep_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range