Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420528568	46148028	0	0
DepthKnown_A	420528568	420425857	0	0
RvalidKnown_A	420528568	420425857	0	0
WreadyKnown_A	420528568	420425857	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	46148028	0	0
T1	124558	17217	0	0
T2	74926	7886	0	0
T3	351773	31110	0	0
T4	51508	1618	0	0
T5	319647	31395	0	0
T6	327347	23731	0	0
T13	361879	32388	0	0
T34	141687	241012	0	0
T79	692049	97668	0	0
T80	99055	12168	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420528568	35372563	0	0
DepthKnown_A	420528568	420425857	0	0
RvalidKnown_A	420528568	420425857	0	0
WreadyKnown_A	420528568	420425857	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	35372563	0	0
T1	124558	12027	0	0
T2	74926	5910	0	0
T3	351773	27282	0	0
T4	51508	896	0	0
T5	319647	25583	0	0
T6	327347	15996	0	0
T13	361879	28606	0	0
T34	141687	209993	0	0
T79	692049	94535	0	0
T80	99055	9488	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420528568	33031022	0	0
DepthKnown_A	420528568	420425857	0	0
RvalidKnown_A	420528568	420425857	0	0
WreadyKnown_A	420528568	420425857	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	33031022	0	0
T1	124558	6470	0	0
T2	74926	4656	0	0
T3	351773	41870	0	0
T4	51508	339	0	0
T5	319647	19680	0	0
T6	327347	12964	0	0
T13	361879	42855	0	0
T34	141687	163291	0	0
T79	692049	91527	0	0
T80	99055	7722	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420528568	27401074	0	0
DepthKnown_A	420528568	420425857	0	0
RvalidKnown_A	420528568	420425857	0	0
WreadyKnown_A	420528568	420425857	0	0
gen_passthru_fifo.paramCheckPass	959	959	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	27401074	0	0
T1	124558	6193	0	0
T2	74926	4539	0	0
T3	351773	41666	0	0
T4	51508	264	0	0
T5	319647	19272	0	0
T6	327347	12452	0	0
T13	361879	42650	0	0
T34	141687	162862	0	0
T79	692049	91373	0	0
T80	99055	7542	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	420425857	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490166007	87707	0	0
DepthKnown_A	490166007	490051474	0	0
RvalidKnown_A	490166007	490051474	0	0
WreadyKnown_A	490166007	490051474	0	0
gen_passthru_fifo.paramCheckPass	2849	2849	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	87707	0	0
T1	124558	26	0	0
T2	74926	13	0	0
T3	351773	53	0	0
T4	51508	3	0	0
T5	319647	49	0	0
T6	327347	68	0	0
T13	361879	53	0	0
T34	141687	42	0	0
T79	692049	13	0	0
T80	99055	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2849	2849	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490166007	89593	0	0
DepthKnown_A	490166007	490051474	0	0
RvalidKnown_A	490166007	490051474	0	0
WreadyKnown_A	490166007	490051474	0	0
gen_passthru_fifo.paramCheckPass	2849	2849	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	89593	0	0
T1	124558	26	0	0
T2	74926	13	0	0
T3	351773	53	0	0
T4	51508	3	0	0
T5	319647	49	0	0
T6	327347	68	0	0
T13	361879	53	0	0
T34	141687	42	0	0
T79	692049	13	0	0
T80	99055	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2849	2849	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490166007	49430	0	0
DepthKnown_A	490166007	490051474	0	0
RvalidKnown_A	490166007	490051474	0	0
WreadyKnown_A	490166007	490051474	0	0
gen_passthru_fifo.paramCheckPass	2849	2849	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	49430	0	0
T1	124558	23	0	0
T2	74926	12	0	0
T3	351773	52	0	0
T4	51508	3	0	0
T5	319647	46	0	0
T6	327347	64	0	0
T13	361879	52	0	0
T34	141687	40	0	0
T79	692049	12	0	0
T80	99055	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2849	2849	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490166007	49429	0	0
DepthKnown_A	490166007	490051474	0	0
RvalidKnown_A	490166007	490051474	0	0
WreadyKnown_A	490166007	490051474	0	0
gen_passthru_fifo.paramCheckPass	2849	2849	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	49429	0	0
T1	124558	23	0	0
T2	74926	12	0	0
T3	351773	52	0	0
T4	51508	3	0	0
T5	319647	46	0	0
T6	327347	64	0	0
T13	361879	52	0	0
T34	141687	40	0	0
T79	692049	12	0	0
T80	99055	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2849	2849	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490166007	38277	0	0
DepthKnown_A	490166007	490051474	0	0
RvalidKnown_A	490166007	490051474	0	0
WreadyKnown_A	490166007	490051474	0	0
gen_passthru_fifo.paramCheckPass	2849	2849	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	38277	0	0
T1	124558	3	0	0
T2	74926	1	0	0
T3	351773	1	0	0
T4	51508	0	0	0
T5	319647	3	0	0
T6	327347	4	0	0
T13	361879	1	0	0
T34	141687	2	0	0
T60	0	15	0	0
T79	692049	1	0	0
T80	99055	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2849	2849	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490166007	40164	0	0
DepthKnown_A	490166007	490051474	0	0
RvalidKnown_A	490166007	490051474	0	0
WreadyKnown_A	490166007	490051474	0	0
gen_passthru_fifo.paramCheckPass	2849	2849	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	40164	0	0
T1	124558	3	0	0
T2	74926	1	0	0
T3	351773	1	0	0
T4	51508	0	0	0
T5	319647	3	0	0
T6	327347	4	0	0
T13	361879	1	0	0
T34	141687	2	0	0
T60	0	15	0	0
T79	692049	1	0	0
T80	99055	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490166007	490051474	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2849	2849	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0