Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.44	96.47	89.29	100.00		100.00	71.43	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	841057136	3798	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	841057136	3798	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	3798	0	0
T1	124558	2	0	0
T2	74926	1	0	0
T3	351773	1	0	0
T4	51508	0	0	0
T5	319647	3	0	0
T6	327347	4	0	0
T13	361879	1	0	0
T20	192382	0	0	0
T34	141687	2	0	0
T60	0	10	0	0
T79	692049	1	0	0
T80	99055	2	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	4	0	0
T135	0	4	0	0
T136	0	11	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T251	0	7	0	0
T260	0	4	0	0
T261	0	7	0	0
T262	73248	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	3798	0	0
T1	124558	2	0	0
T2	74926	1	0	0
T3	351773	1	0	0
T4	51508	0	0	0
T5	319647	3	0	0
T6	327347	4	0	0
T13	361879	1	0	0
T20	192382	0	0	0
T34	141687	2	0	0
T60	0	10	0	0
T79	692049	1	0	0
T80	99055	2	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	4	0	0
T135	0	4	0	0
T136	0	11	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T251	0	7	0	0
T260	0	4	0	0
T261	0	7	0	0
T262	73248	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	420528568	37	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	420528568	37	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	37	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	4	0	0
T135	0	4	0	0
T136	0	11	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T251	0	7	0	0
T260	0	4	0	0
T261	0	7	0	0
T262	73248	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	37	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	4	0	0
T135	0	4	0	0
T136	0	11	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T251	0	7	0	0
T260	0	4	0	0
T261	0	7	0	0
T262	73248	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	420528568	3761	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	420528568	3761	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	3761	0	0
T1	124558	2	0	0
T2	74926	1	0	0
T3	351773	1	0	0
T4	51508	0	0	0
T5	319647	3	0	0
T6	327347	4	0	0
T13	361879	1	0	0
T34	141687	2	0	0
T60	0	10	0	0
T79	692049	1	0	0
T80	99055	2	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	3761	0	0
T1	124558	2	0	0
T2	74926	1	0	0
T3	351773	1	0	0
T4	51508	0	0	0
T5	319647	3	0	0
T6	327347	4	0	0
T13	361879	1	0	0
T34	141687	2	0	0
T60	0	10	0	0
T79	692049	1	0	0
T80	99055	2	0	0