Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T134,T20,T135
0	1	Covered	T134,T135,T260
1	0	Covered	T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T134,T20,T135
1	Covered	T134,T20,T135

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T134,T20,T135
1	Covered	T134,T20,T135

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T134,T135,T260
1	1	Covered	T134,T20,T135

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T134,T20,T135
1	0	Covered	T134,T20,T135
1	1	Covered	T134,T135,T260

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T134,T20,T135

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T134,T20,T135
0	Covered	T134,T20,T135

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T134,T20,T135
0	Covered	T134,T20,T135

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	841057136	822327586	0	0
CheckNGreaterZero_A	1918	1918	0	0
GntImpliesReady_A	841057136	5429	0	0
GntImpliesValid_A	841057136	5429	0	0
GrantKnown_A	841057136	822327586	0	0
IdxKnown_A	841057136	822327586	0	0
IndexIsCorrect_A	841057136	5429	0	0
NoReadyValidNoGrant_A	841057136	0	0	0
Priority_A	841057136	5429	0	0
ReadyAndValidImplyGrant_A	841057136	5429	0	0
ReqAndReadyImplyGrant_A	841057136	5429	0	0
ReqImpliesValid_A	841057136	5429	0	0
ValidKnown_A	841057136	822327586	0	0
gen_data_port_assertion.DataFlow_A	841057136	5429	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	822327586	0	0
T1	249116	249014	0	0
T2	149852	149742	0	0
T3	703546	703436	0	0
T4	103016	102790	0	0
T5	639294	638866	0	0
T6	654694	653988	0	0
T13	723758	723642	0	0
T34	283374	283350	0	0
T79	1384098	1383974	0	0
T80	198110	197986	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1918	1918	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T13	2	2	0	0
T34	2	2	0	0
T79	2	2	0	0
T80	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	5429	0	0
T20	384764	0	0	0
T103	1451994	0	0	0
T119	335702	0	0	0
T120	73974	0	0	0
T134	156152	1803	0	0
T135	0	1808	0	0
T144	137958	0	0	0
T152	433512	0	0	0
T155	359218	0	0	0
T224	197138	0	0	0
T260	0	1818	0	0
T262	146496	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	5429	0	0
T20	384764	0	0	0
T103	1451994	0	0	0
T119	335702	0	0	0
T120	73974	0	0	0
T134	156152	1803	0	0
T135	0	1808	0	0
T144	137958	0	0	0
T152	433512	0	0	0
T155	359218	0	0	0
T224	197138	0	0	0
T260	0	1818	0	0
T262	146496	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	822327586	0	0
T1	249116	249014	0	0
T2	149852	149742	0	0
T3	703546	703436	0	0
T4	103016	102790	0	0
T5	639294	638866	0	0
T6	654694	653988	0	0
T13	723758	723642	0	0
T34	283374	283350	0	0
T79	1384098	1383974	0	0
T80	198110	197986	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	822327586	0	0
T1	249116	249014	0	0
T2	149852	149742	0	0
T3	703546	703436	0	0
T4	103016	102790	0	0
T5	639294	638866	0	0
T6	654694	653988	0	0
T13	723758	723642	0	0
T34	283374	283350	0	0
T79	1384098	1383974	0	0
T80	198110	197986	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	5429	0	0
T20	384764	0	0	0
T103	1451994	0	0	0
T119	335702	0	0	0
T120	73974	0	0	0
T134	156152	1803	0	0
T135	0	1808	0	0
T144	137958	0	0	0
T152	433512	0	0	0
T155	359218	0	0	0
T224	197138	0	0	0
T260	0	1818	0	0
T262	146496	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	5429	0	0
T20	384764	0	0	0
T103	1451994	0	0	0
T119	335702	0	0	0
T120	73974	0	0	0
T134	156152	1803	0	0
T135	0	1808	0	0
T144	137958	0	0	0
T152	433512	0	0	0
T155	359218	0	0	0
T224	197138	0	0	0
T260	0	1818	0	0
T262	146496	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	5429	0	0
T20	384764	0	0	0
T103	1451994	0	0	0
T119	335702	0	0	0
T120	73974	0	0	0
T134	156152	1803	0	0
T135	0	1808	0	0
T144	137958	0	0	0
T152	433512	0	0	0
T155	359218	0	0	0
T224	197138	0	0	0
T260	0	1818	0	0
T262	146496	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	5429	0	0
T20	384764	0	0	0
T103	1451994	0	0	0
T119	335702	0	0	0
T120	73974	0	0	0
T134	156152	1803	0	0
T135	0	1808	0	0
T144	137958	0	0	0
T152	433512	0	0	0
T155	359218	0	0	0
T224	197138	0	0	0
T260	0	1818	0	0
T262	146496	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	5429	0	0
T20	384764	0	0	0
T103	1451994	0	0	0
T119	335702	0	0	0
T120	73974	0	0	0
T134	156152	1803	0	0
T135	0	1808	0	0
T144	137958	0	0	0
T152	433512	0	0	0
T155	359218	0	0	0
T224	197138	0	0	0
T260	0	1818	0	0
T262	146496	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	822327586	0	0
T1	249116	249014	0	0
T2	149852	149742	0	0
T3	703546	703436	0	0
T4	103016	102790	0	0
T5	639294	638866	0	0
T6	654694	653988	0	0
T13	723758	723642	0	0
T34	283374	283350	0	0
T79	1384098	1383974	0	0
T80	198110	197986	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841057136	5429	0	0
T20	384764	0	0	0
T103	1451994	0	0	0
T119	335702	0	0	0
T120	73974	0	0	0
T134	156152	1803	0	0
T135	0	1808	0	0
T144	137958	0	0	0
T152	433512	0	0	0
T155	359218	0	0	0
T224	197138	0	0	0
T260	0	1818	0	0
T262	146496	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T134,T20,T135
0	1	Covered	T134,T135,T260
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T134,T135,T260
1	Covered	T134,T20,T135

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T134,T135,T260
1	Covered	T134,T20,T135

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T134,T135,T260
1	1	Covered	T134,T135,T260

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T134,T20,T135
1	0	Covered	T134,T135,T260
1	1	Covered	T134,T135,T260

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T134,T135,T260

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T134,T20,T135
0	Covered	T134,T135,T260

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T134,T20,T135
0	Covered	T134,T135,T260

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420528568	411163793	0	0
CheckNGreaterZero_A	959	959	0	0
GntImpliesReady_A	420528568	4397	0	0
GntImpliesValid_A	420528568	4397	0	0
GrantKnown_A	420528568	411163793	0	0
IdxKnown_A	420528568	411163793	0	0
IndexIsCorrect_A	420528568	4397	0	0
NoReadyValidNoGrant_A	420528568	0	0	0
Priority_A	420528568	4397	0	0
ReadyAndValidImplyGrant_A	420528568	4397	0	0
ReqAndReadyImplyGrant_A	420528568	4397	0	0
ReqImpliesValid_A	420528568	4397	0	0
ValidKnown_A	420528568	411163793	0	0
gen_data_port_assertion.DataFlow_A	420528568	4397	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	411163793	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	4397	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	1459	0	0
T135	0	1464	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	1474	0	0
T262	73248	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	4397	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	1459	0	0
T135	0	1464	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	1474	0	0
T262	73248	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	411163793	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	411163793	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	4397	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	1459	0	0
T135	0	1464	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	1474	0	0
T262	73248	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	4397	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	1459	0	0
T135	0	1464	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	1474	0	0
T262	73248	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	4397	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	1459	0	0
T135	0	1464	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	1474	0	0
T262	73248	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	4397	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	1459	0	0
T135	0	1464	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	1474	0	0
T262	73248	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	4397	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	1459	0	0
T135	0	1464	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	1474	0	0
T262	73248	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	411163793	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	4397	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	1459	0	0
T135	0	1464	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	1474	0	0
T262	73248	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T134,T20,T135
0	1	Covered	T134,T135,T260
1	0	Covered	T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T134,T20,T135
1	Covered	T134,T20,T135

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T134,T20,T135
1	Covered	T134,T20,T135

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T134,T135,T260
1	1	Covered	T134,T20,T135

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T134,T20,T135
1	0	Covered	T134,T20,T135
1	1	Covered	T134,T135,T260

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T134,T20,T135

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T134,T20,T135
0	Covered	T134,T20,T135

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T134,T20,T135
0	Covered	T134,T20,T135

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420528568	411163793	0	0
CheckNGreaterZero_A	959	959	0	0
GntImpliesReady_A	420528568	1032	0	0
GntImpliesValid_A	420528568	1032	0	0
GrantKnown_A	420528568	411163793	0	0
IdxKnown_A	420528568	411163793	0	0
IndexIsCorrect_A	420528568	1032	0	0
NoReadyValidNoGrant_A	420528568	0	0	0
Priority_A	420528568	1032	0	0
ReadyAndValidImplyGrant_A	420528568	1032	0	0
ReqAndReadyImplyGrant_A	420528568	1032	0	0
ReqImpliesValid_A	420528568	1032	0	0
ValidKnown_A	420528568	411163793	0	0
gen_data_port_assertion.DataFlow_A	420528568	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	411163793	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	959	959	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T34	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	1032	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	344	0	0
T135	0	344	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	344	0	0
T262	73248	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	1032	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	344	0	0
T135	0	344	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	344	0	0
T262	73248	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	411163793	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	411163793	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	1032	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	344	0	0
T135	0	344	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	344	0	0
T262	73248	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	1032	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	344	0	0
T135	0	344	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	344	0	0
T262	73248	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	1032	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	344	0	0
T135	0	344	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	344	0	0
T262	73248	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	1032	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	344	0	0
T135	0	344	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	344	0	0
T262	73248	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	1032	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	344	0	0
T135	0	344	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	344	0	0
T262	73248	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	411163793	0	0
T1	124558	124507	0	0
T2	74926	74871	0	0
T3	351773	351718	0	0
T4	51508	51395	0	0
T5	319647	319433	0	0
T6	327347	326994	0	0
T13	361879	361821	0	0
T34	141687	141675	0	0
T79	692049	691987	0	0
T80	99055	98993	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420528568	1032	0	0
T20	192382	0	0	0
T103	725997	0	0	0
T119	167851	0	0	0
T120	36987	0	0	0
T134	78076	344	0	0
T135	0	344	0	0
T144	68979	0	0	0
T152	216756	0	0	0
T155	179609	0	0	0
T224	98569	0	0	0
T260	0	344	0	0
T262	73248	0	0	0