Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3805497	1			T77	8701		T81	485		T82	6600
values[2]	777050	1			T77	1194		T81	112		T82	1593
values[3]	116538	1			T77	105		T82	296		T230	1
values[4]	61545	1			T77	50		T82	164		T230	2
values[5]	40932	1			T77	37		T82	94		T230	5
values[6]	30498	1			T77	34		T82	65		T230	5
values[7]	24542	1			T77	36		T82	56		T230	1
values[8]	21042	1			T77	56		T82	35		T230	1
values[9]	18660	1			T77	48		T82	24		T230	3
values[10]	16826	1			T77	34		T82	22		T230	3
values[11]	15618	1			T77	28		T82	17		T230	3
values[12]	14632	1			T77	34		T82	14		T230	4
values[13]	14236	1			T77	40		T82	11		T230	2
values[14]	13217	1			T77	45		T82	5		T230	1
values[15]	12403	1			T77	65		T82	8		T230	1
values[16]	12045	1			T77	76		T82	7		T230	1
values[17]	11755	1			T77	52		T82	6		T230	2
values[18]	11279	1			T77	30		T82	2		T230	6
values[19]	11154	1			T77	47		T82	5		T230	2
values[20]	10717	1			T77	34		T82	11		T230	2
values[21]	10361	1			T77	26		T82	3		T230	1
values[22]	9930	1			T77	28		T82	4		T230	1
values[23]	9653	1			T77	36		T82	7		T230	1
values[24]	9283	1			T77	40		T82	6		T230	3
values[25]	8910	1			T77	29		T82	2		T230	1
values[26]	8531	1			T77	33		T82	13		T230	2
values[27]	8185	1			T77	36		T82	16		T230	3
values[28]	7780	1			T77	33		T82	11		T230	1
values[29]	7332	1			T77	23		T82	13		T230	3
values[30]	6791	1			T77	36		T82	3		T230	6
values[31]	6470	1			T77	25		T82	2		T230	6
values[32]	6151	1			T77	16		T82	5		T230	2
values[33]	5841	1			T77	18		T82	2		T230	1
values[34]	5383	1			T77	11		T82	1		T230	5
values[35]	5001	1			T77	5		T230	6		T491	24
values[36]	4607	1			T77	4		T230	2		T491	15
values[37]	4546	1			T77	5		T230	1		T491	27
values[38]	4253	1			T77	4		T230	1		T491	25
values[39]	4207	1			T77	4		T230	1		T491	25
values[40]	4060	1			T77	3		T230	5		T491	24
values[41]	3916	1			T77	3		T230	4		T491	23
values[42]	3846	1			T77	4		T230	4		T491	20
values[43]	3789	1			T77	4		T230	3		T491	28
values[44]	3663	1			T77	5		T230	2		T491	31
values[45]	3557	1			T77	4		T230	1		T491	30
values[46]	3564	1			T77	4		T230	2		T491	28
values[47]	3596	1			T77	4		T230	6		T491	17
values[48]	3451	1			T77	4		T230	4		T491	17
values[49]	3439	1			T77	6		T230	3		T491	27
values[50]	3302	1			T77	4		T230	1		T491	21
values[51]	3265	1			T77	9		T230	1		T491	17
values[52]	3206	1			T77	7		T230	5		T491	17
values[53]	3193	1			T77	3		T230	5		T491	20
values[54]	3132	1			T230	2		T491	16		T662	2
values[55]	3069	1			T230	1		T491	16		T662	2
values[56]	3016	1			T230	1		T491	16		T662	2
values[57]	2927	1			T230	1		T491	17		T662	2
values[58]	2881	1			T230	1		T491	14		T662	2
values[59]	2945	1			T230	1		T491	18		T662	2
values[60]	2853	1			T230	3		T491	14		T662	2
values[61]	3205	1			T230	7		T491	24		T662	2
values[62]	5193	1			T230	19		T491	56		T662	2
values[63]	20638	1			T230	38		T491	154		T662	2
values[64]	240521	1			T230	61		T491	216		T662	380

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4945748	1			T77	9811		T81	596		T82	9274
values[2]	811603	1			T77	1533		T81	166		T82	1288
values[3]	78229	1			T77	30		T81	4		T82	95
values[4]	14025	1			T77	4		T81	1		T82	17
values[5]	5409	1			T77	3		T82	2		T231	2
values[6]	3282	1			T77	3		T82	1		T231	1
values[7]	2482	1			T77	3		T82	1		T786	17
values[8]	2208	1			T77	1		T82	2		T786	6
values[9]	1971	1			T77	1		T786	3		T425	17
values[10]	1764	1			T77	1		T425	14		T548	8
values[11]	1612	1			T77	1		T425	10		T548	3
values[12]	1558	1			T77	6		T425	15		T548	1
values[13]	1535	1			T77	2		T425	1		T548	1
values[14]	1403	1			T77	1		T425	4		T548	1
values[15]	1362	1			T77	4		T425	5		T548	1
values[16]	1258	1			T77	1		T425	1		T548	2
values[17]	1178	1			T77	3		T425	2		T548	4
values[18]	1073	1			T77	1		T425	9		T548	1
values[19]	1093	1			T77	2		T425	4		T548	1
values[20]	1078	1			T77	2		T425	2		T548	2
values[21]	960	1			T77	2		T548	1		T401	5
values[22]	987	1			T77	10		T548	1		T401	4
values[23]	969	1			T77	2		T548	1		T401	5
values[24]	897	1			T77	1		T548	1		T401	2
values[25]	842	1			T77	2		T548	3		T401	2
values[26]	800	1			T77	1		T548	1		T401	2
values[27]	740	1			T77	3		T548	3		T401	1
values[28]	688	1			T77	2		T548	1		T401	2
values[29]	698	1			T77	1		T548	1		T401	2
values[30]	685	1			T77	2		T548	2		T401	2
values[31]	683	1			T77	4		T548	4		T401	2
values[32]	631	1			T77	2		T548	4		T401	3
values[33]	648	1			T77	2		T548	2		T401	2
values[34]	601	1			T77	1		T548	1		T401	2
values[35]	555	1			T77	1		T548	1		T401	4
values[36]	514	1			T77	1		T548	2		T401	5
values[37]	524	1			T77	1		T548	1		T405	1
values[38]	498	1			T77	2		T548	1		T405	1
values[39]	484	1			T77	5		T548	1		T405	1
values[40]	481	1			T77	3		T548	1		T405	1
values[41]	470	1			T77	4		T548	1		T405	1
values[42]	461	1			T77	1		T548	1		T405	1
values[43]	457	1			T77	4		T548	1		T405	1
values[44]	465	1			T77	1		T548	1		T405	1
values[45]	448	1			T77	2		T548	2		T405	1
values[46]	460	1			T77	1		T548	2		T405	1
values[47]	424	1			T77	1		T548	1		T405	1
values[48]	421	1			T77	1		T548	4		T405	1
values[49]	384	1			T77	1		T548	4		T405	1
values[50]	380	1			T77	2		T548	1		T405	1
values[51]	385	1			T77	1		T548	1		T405	1
values[52]	390	1			T77	5		T548	1		T405	1
values[53]	416	1			T77	1		T548	4		T405	1
values[54]	404	1			T77	1		T548	3		T405	1
values[55]	376	1			T77	5		T548	3		T405	1
values[56]	388	1			T77	1		T548	2		T405	1
values[57]	381	1			T77	3		T548	2		T405	1
values[58]	366	1			T77	1		T548	4		T405	1
values[59]	356	1			T77	1		T548	4		T405	1
values[60]	379	1			T77	1		T548	3		T405	1
values[61]	456	1			T77	3		T548	1		T405	1
values[62]	817	1			T77	2		T548	3		T405	1
values[63]	3833	1			T77	8		T548	19		T405	1
values[64]	25970	1			T77	72		T548	73		T405	179

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	614763	1			T77	386		T81	5		T82	146
values[2]	2699758	1			T77	8514		T81	484		T82	3070
values[3]	1192151	1			T77	1422		T81	129		T82	5492
values[4]	153432	1			T77	90		T82	303		T230	82
values[5]	80204	1			T77	77		T82	138		T230	27
values[6]	52352	1			T77	42		T82	82		T230	11
values[7]	38198	1			T77	78		T82	52		T230	3
values[8]	31062	1			T77	64		T82	46		T230	1
values[9]	26473	1			T77	30		T82	69		T230	1
values[10]	23215	1			T77	34		T82	46		T230	2
values[11]	20768	1			T77	51		T82	29		T230	1
values[12]	19024	1			T77	74		T82	15		T230	1
values[13]	17518	1			T77	33		T82	6		T230	3
values[14]	16396	1			T77	30		T82	2		T230	2
values[15]	15518	1			T77	19		T82	1		T230	1
values[16]	14824	1			T77	43		T82	1		T230	5
values[17]	14263	1			T77	37		T82	1		T230	1
values[18]	13411	1			T77	32		T82	1		T230	1
values[19]	12969	1			T77	23		T230	5		T491	23
values[20]	12656	1			T77	34		T230	5		T491	26
values[21]	12172	1			T77	42		T230	1		T491	19
values[22]	11460	1			T77	50		T230	2		T491	33
values[23]	10849	1			T77	50		T230	6		T491	28
values[24]	10516	1			T77	49		T230	2		T491	33
values[25]	10043	1			T77	61		T230	3		T491	46
values[26]	9571	1			T77	43		T230	8		T491	52
values[27]	9001	1			T77	26		T230	9		T491	63
values[28]	8791	1			T77	46		T230	3		T491	51
values[29]	8631	1			T77	32		T230	2		T491	55
values[30]	8050	1			T77	11		T230	1		T491	37
values[31]	7491	1			T77	5		T230	3		T491	17
values[32]	7040	1			T77	4		T230	1		T491	18
values[33]	6554	1			T77	8		T230	1		T491	25
values[34]	5872	1			T77	5		T230	1		T491	22
values[35]	5381	1			T77	4		T230	2		T491	11
values[36]	5122	1			T77	4		T230	3		T491	12
values[37]	4903	1			T77	6		T230	2		T491	14
values[38]	4544	1			T77	8		T230	1		T491	19
values[39]	4375	1			T77	6		T230	2		T491	27
values[40]	4287	1			T77	6		T230	3		T491	16
values[41]	4100	1			T77	5		T230	2		T491	29
values[42]	4054	1			T77	5		T230	1		T491	35
values[43]	4043	1			T77	7		T230	2		T491	29
values[44]	3965	1			T77	4		T230	1		T491	18
values[45]	3915	1			T77	7		T230	4		T491	16
values[46]	3818	1			T77	7		T230	9		T491	15
values[47]	3772	1			T77	6		T230	12		T491	20
values[48]	3518	1			T77	15		T230	6		T491	21
values[49]	3748	1			T77	7		T230	5		T491	27
values[50]	3830	1			T77	5		T230	1		T491	33
values[51]	3654	1			T77	3		T230	1		T491	16
values[52]	3447	1			T77	6		T230	1		T491	13
values[53]	3367	1			T77	4		T230	3		T491	19
values[54]	3289	1			T77	9		T230	1		T491	22
values[55]	3179	1			T77	7		T230	1		T491	19
values[56]	3358	1			T77	6		T230	1		T491	20
values[57]	3232	1			T77	2		T230	2		T491	20
values[58]	3137	1			T77	2		T230	2		T491	26
values[59]	2991	1			T77	4		T230	2		T491	25
values[60]	3086	1			T77	1		T230	6		T491	15
values[61]	3233	1			T77	1		T230	2		T491	18
values[62]	4946	1			T77	1		T230	6		T491	44
values[63]	20930	1			T77	3		T230	27		T491	123
values[64]	229456	1			T77	86		T230	42		T491	215