Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2331630	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26915180

1

T1

4361

T2

3735

T3

3580

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19137312	1			T1	1343		T2	1018		T3	910
values[0x0]	8265095	1			T1	3018		T2	2717		T3	2670
values[0x1]	1844403	1			T1	161		T2	140		T3	141

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	610696	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

28636114

1

T1

4522

T2

3875

T3

3721

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13498235	1			T1	2261		T2	1938		T3	1861
valid_sources[0x01]	13498322	1			T1	2261		T2	1937		T3	1860
valid_sources[0x02]	35276	1			T79	2		T411	1		T76	31
valid_sources[0x03]	36548	1			T51	2		T76	20		T78	52
valid_sources[0x04]	37044	1			T51	2		T76	29		T78	27
valid_sources[0x05]	35179	1			T76	17		T78	24		T347	65
valid_sources[0x06]	36467	1			T51	6		T76	32		T78	25
valid_sources[0x07]	35736	1			T79	1		T411	1		T76	23
valid_sources[0x08]	35534	1			T51	2		T76	17		T78	26
valid_sources[0x09]	36892	1			T76	23		T78	35		T347	92
valid_sources[0x0a]	36122	1			T411	1		T76	14		T78	20
valid_sources[0x0b]	35699	1			T411	1		T76	17		T78	55
valid_sources[0x0c]	36293	1			T411	1		T51	1		T76	12
valid_sources[0x0d]	35699	1			T76	21		T78	43		T347	94
valid_sources[0x0e]	35590	1			T411	1		T76	9		T78	18
valid_sources[0x0f]	35959	1			T76	16		T78	22		T347	90
valid_sources[0x10]	37249	1			T61	39		T411	2		T51	1
valid_sources[0x11]	36725	1			T76	21		T78	20		T347	75
valid_sources[0x12]	36709	1			T51	1		T76	33		T78	19
valid_sources[0x13]	37461	1			T76	14		T78	15		T347	74
valid_sources[0x14]	35086	1			T76	29		T78	22		T347	72
valid_sources[0x15]	36754	1			T76	27		T78	32		T347	55
valid_sources[0x16]	36212	1			T79	7		T411	1		T76	27
valid_sources[0x17]	36179	1			T79	2		T76	11		T78	23
valid_sources[0x18]	36460	1			T79	1		T76	15		T78	18
valid_sources[0x19]	36402	1			T51	2		T76	15		T78	23
valid_sources[0x1a]	36498	1			T76	19		T78	20		T347	73
valid_sources[0x1b]	36261	1			T76	15		T78	10		T347	83
valid_sources[0x1c]	37003	1			T411	4		T51	4		T76	10
valid_sources[0x1d]	35237	1			T79	1		T51	1		T76	22
valid_sources[0x1e]	36927	1			T411	2		T51	2		T76	13
valid_sources[0x1f]	36152	1			T79	1		T76	21		T78	25
valid_sources[0x20]	36297	1			T76	21		T78	20		T347	82

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18445113

1

T1

1343

T2

1018

T3

910

values[0x0]

all_enables

biggest_size

8228841

1

T1

3018

T2

2717

T3

2670

values[0x1]

all_enables

biggest_size

241226

1

T61

23

T79

13

T80

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2978040	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

471272

1

T77

1484

T81

69

T82

1199

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1166151	1			T77	3779		T81	200		T82	3124
values[0x0]	1114380	1			T77	3653		T81	198		T82	2964
values[0x1]	1168781	1			T77	3790		T81	199		T82	3028

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2307458	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1141854

1

T77

3721

T81

187

T82

3038

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52824	1			T77	243		T81	10		T82	168
valid_sources[0x01]	54125	1			T77	179		T81	13		T82	142
valid_sources[0x02]	52859	1			T77	177		T81	4		T82	140
valid_sources[0x03]	55001	1			T77	437		T82	128		T231	3
valid_sources[0x04]	53635	1			T77	139		T81	4		T82	140
valid_sources[0x05]	56064	1			T77	194		T81	13		T82	139
valid_sources[0x06]	53672	1			T77	146		T81	18		T82	137
valid_sources[0x07]	53374	1			T77	124		T81	3		T82	148
valid_sources[0x08]	53068	1			T77	222		T82	123		T231	4
valid_sources[0x09]	55630	1			T77	272		T81	13		T82	115
valid_sources[0x0a]	55287	1			T77	292		T82	162		T231	3
valid_sources[0x0b]	53975	1			T77	205		T81	21		T82	119
valid_sources[0x0c]	54158	1			T77	123		T81	16		T82	155
valid_sources[0x0d]	52884	1			T77	156		T82	155		T231	1
valid_sources[0x0e]	54125	1			T77	81		T81	16		T82	107
valid_sources[0x0f]	54268	1			T77	115		T82	167		T231	2
valid_sources[0x10]	54632	1			T77	182		T82	143		T231	2
valid_sources[0x11]	53218	1			T77	170		T81	7		T82	138
valid_sources[0x12]	53678	1			T77	269		T81	12		T82	149
valid_sources[0x13]	53577	1			T77	178		T81	20		T82	167
valid_sources[0x14]	53721	1			T77	148		T81	4		T82	162
valid_sources[0x15]	54158	1			T77	359		T81	4		T82	157
valid_sources[0x16]	54066	1			T77	143		T82	114		T231	3
valid_sources[0x17]	54482	1			T77	185		T81	15		T82	165
valid_sources[0x18]	53883	1			T77	107		T81	7		T82	113
valid_sources[0x19]	54393	1			T77	133		T81	9		T82	165
valid_sources[0x1a]	53670	1			T77	105		T81	2		T82	108
valid_sources[0x1b]	54066	1			T77	188		T81	23		T82	152
valid_sources[0x1c]	53928	1			T77	92		T81	9		T82	146
valid_sources[0x1d]	54281	1			T77	62		T81	2		T82	140
valid_sources[0x1e]	53129	1			T77	83		T81	9		T82	126
valid_sources[0x1f]	54354	1			T77	172		T82	143		T231	1
valid_sources[0x20]	54053	1			T77	171		T81	21		T82	188

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49283

1

T77

148

T81

8

T82

110

values[0x0]

all_enables

biggest_size

372656

1

T77

1199

T81

53

T82

959

values[0x1]

all_enables

biggest_size

49333

1

T77

137

T81

8

T82

130

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3162937	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

515264

1

T77

1641

T81

112

T82

1524

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1257929	1			T77	3896		T81	244		T82	3631
values[0x0]	1161251	1			T77	3723		T81	260		T82	3477
values[0x1]	1259021	1			T77	3965		T81	263		T82	3563

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2428654	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1249547

1

T77

3968

T81

253

T82

3609

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56951	1			T77	202		T81	7		T82	279
valid_sources[0x01]	57699	1			T77	97		T81	1		T82	229
valid_sources[0x02]	57252	1			T77	320		T81	24		T82	72
valid_sources[0x03]	56507	1			T77	153		T81	10		T82	123
valid_sources[0x04]	56508	1			T77	119		T81	9		T82	207
valid_sources[0x05]	57607	1			T77	62		T81	18		T82	139
valid_sources[0x06]	57373	1			T77	173		T81	16		T82	150
valid_sources[0x07]	56589	1			T77	196		T81	19		T82	248
valid_sources[0x08]	57040	1			T77	182		T81	14		T82	110
valid_sources[0x09]	58178	1			T77	168		T81	20		T82	196
valid_sources[0x0a]	57959	1			T77	200		T81	6		T82	259
valid_sources[0x0b]	58027	1			T77	208		T81	16		T82	200
valid_sources[0x0c]	56494	1			T77	164		T81	14		T82	217
valid_sources[0x0d]	58091	1			T77	159		T81	15		T82	135
valid_sources[0x0e]	58879	1			T77	118		T81	10		T82	246
valid_sources[0x0f]	58694	1			T77	195		T81	22		T82	215
valid_sources[0x10]	57762	1			T77	175		T81	25		T82	194
valid_sources[0x11]	57151	1			T77	167		T81	8		T82	119
valid_sources[0x12]	57973	1			T77	101		T81	26		T82	197
valid_sources[0x13]	56469	1			T77	205		T81	13		T82	206
valid_sources[0x14]	57141	1			T77	150		T81	12		T82	164
valid_sources[0x15]	57850	1			T77	232		T81	6		T82	120
valid_sources[0x16]	56991	1			T77	153		T81	2		T82	125
valid_sources[0x17]	57047	1			T77	135		T81	9		T82	142
valid_sources[0x18]	57596	1			T77	187		T81	1		T82	64
valid_sources[0x19]	58810	1			T77	206		T81	15		T82	204
valid_sources[0x1a]	58388	1			T77	179		T81	21		T82	105
valid_sources[0x1b]	57243	1			T77	220		T81	32		T82	158
valid_sources[0x1c]	56765	1			T77	146		T81	21		T82	187
valid_sources[0x1d]	57457	1			T77	199		T81	19		T82	206
valid_sources[0x1e]	56620	1			T77	103		T81	3		T82	149
valid_sources[0x1f]	57894	1			T77	209		T81	11		T82	184
valid_sources[0x20]	57766	1			T77	137		T81	17		T82	210

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53827

1

T77

164

T81

13

T82

171

values[0x0]

all_enables

biggest_size

407651

1

T77

1296

T81

89

T82

1198

values[0x1]

all_enables

biggest_size

53786

1

T77

181

T81

10

T82

155

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2996590	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

474347

1

T77

1596

T81

96

T82

1288

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1175135	1			T77	3999		T81	208		T82	3303
values[0x0]	1120907	1			T77	3902		T81	210		T82	3026
values[0x1]	1174895	1			T77	3881		T81	200		T82	3153

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2319293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1151644

1

T77

3830

T81

205

T82

3150

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53685	1			T77	141		T81	9		T82	181
valid_sources[0x01]	53780	1			T77	166		T81	12		T82	169
valid_sources[0x02]	54498	1			T77	159		T81	10		T82	165
valid_sources[0x03]	54257	1			T77	149		T81	7		T82	116
valid_sources[0x04]	53956	1			T77	133		T81	7		T82	114
valid_sources[0x05]	55576	1			T77	196		T81	9		T82	129
valid_sources[0x06]	55369	1			T77	368		T81	6		T82	139
valid_sources[0x07]	53719	1			T77	200		T81	9		T82	129
valid_sources[0x08]	53790	1			T77	126		T81	8		T82	174
valid_sources[0x09]	54595	1			T77	301		T81	13		T82	144
valid_sources[0x0a]	54096	1			T77	219		T81	11		T82	165
valid_sources[0x0b]	54870	1			T77	198		T81	8		T82	136
valid_sources[0x0c]	53221	1			T77	152		T81	13		T82	151
valid_sources[0x0d]	54406	1			T77	205		T81	11		T82	158
valid_sources[0x0e]	54443	1			T77	128		T81	7		T82	143
valid_sources[0x0f]	54896	1			T77	270		T81	6		T82	133
valid_sources[0x10]	54181	1			T77	196		T81	8		T82	174
valid_sources[0x11]	54520	1			T77	230		T81	11		T82	151
valid_sources[0x12]	53861	1			T77	196		T81	7		T82	109
valid_sources[0x13]	54172	1			T77	174		T81	11		T82	179
valid_sources[0x14]	53237	1			T77	136		T81	14		T82	135
valid_sources[0x15]	54734	1			T77	279		T81	10		T82	166
valid_sources[0x16]	54815	1			T77	276		T81	14		T82	161
valid_sources[0x17]	54889	1			T77	120		T81	9		T82	181
valid_sources[0x18]	53681	1			T77	161		T81	12		T82	161
valid_sources[0x19]	54104	1			T77	223		T81	13		T82	162
valid_sources[0x1a]	54448	1			T77	153		T81	9		T82	169
valid_sources[0x1b]	54276	1			T77	179		T81	14		T82	202
valid_sources[0x1c]	54233	1			T77	200		T81	13		T82	171
valid_sources[0x1d]	53910	1			T77	141		T81	9		T82	160
valid_sources[0x1e]	53959	1			T77	172		T81	6		T82	157
valid_sources[0x1f]	54247	1			T77	138		T81	12		T82	128
valid_sources[0x20]	54824	1			T77	187		T81	14		T82	137

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49645

1

T77

183

T81

14

T82

130

values[0x0]

all_enables

biggest_size

375180

1

T77

1273

T81

73

T82

1026

values[0x1]

all_enables

biggest_size

49522

1

T77

140

T81

9

T82

132