Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411695447	45006872	0	0
DepthKnown_A	411695447	411594430	0	0
RvalidKnown_A	411695447	411594430	0	0
WreadyKnown_A	411695447	411594430	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	45006872	0	0
T1	172602	12288	0	0
T2	70318	7514	0	0
T3	65405	6322	0	0
T32	212741	13237	0	0
T43	672065	85628	0	0
T59	121008	13873	0	0
T60	252084	31905	0	0
T86	270527	26736	0	0
T87	101342	10377	0	0
T88	91974	10885	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411695447	34523736	0	0
DepthKnown_A	411695447	411594430	0	0
RvalidKnown_A	411695447	411594430	0	0
WreadyKnown_A	411695447	411594430	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	34523736	0	0
T1	172602	8971	0	0
T2	70318	5382	0	0
T3	65405	4633	0	0
T32	212741	9136	0	0
T43	672065	68057	0	0
T59	121008	11766	0	0
T60	252084	27758	0	0
T86	270527	22633	0	0
T87	101342	8157	0	0
T88	91974	8527	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411695447	32463707	0	0
DepthKnown_A	411695447	411594430	0	0
RvalidKnown_A	411695447	411594430	0	0
WreadyKnown_A	411695447	411594430	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	32463707	0	0
T1	172602	4685	0	0
T2	70318	3999	0	0
T3	65405	3835	0	0
T32	212741	7129	0	0
T43	672065	117423	0	0
T59	121008	6686	0	0
T60	252084	15218	0	0
T86	270527	29222	0	0
T87	101342	5754	0	0
T88	91974	6757	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411695447	26991638	0	0
DepthKnown_A	411695447	411594430	0	0
RvalidKnown_A	411695447	411594430	0	0
WreadyKnown_A	411695447	411594430	0	0
gen_passthru_fifo.paramCheckPass	954	954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	26991638	0	0
T1	172602	4522	0	0
T2	70318	3875	0	0
T3	65405	3721	0	0
T32	212741	6877	0	0
T43	672065	59931	0	0
T59	121008	6561	0	0
T60	252084	14962	0	0
T86	270527	29017	0	0
T87	101342	5618	0	0
T88	91974	6567	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	411594430	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483305282	85219	0	0
DepthKnown_A	483305282	483191945	0	0
RvalidKnown_A	483305282	483191945	0	0
WreadyKnown_A	483305282	483191945	0	0
gen_passthru_fifo.paramCheckPass	2845	2845	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	85219	0	0
T1	172602	25	0	0
T2	70318	13	0	0
T3	65405	11	0	0
T32	212741	29	0	0
T43	672065	26	0	0
T59	121008	14	0	0
T60	252084	31	0	0
T86	270527	53	0	0
T87	101342	19	0	0
T88	91974	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2845	2845	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483305282	87487	0	0
DepthKnown_A	483305282	483191945	0	0
RvalidKnown_A	483305282	483191945	0	0
WreadyKnown_A	483305282	483191945	0	0
gen_passthru_fifo.paramCheckPass	2845	2845	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	87487	0	0
T1	172602	25	0	0
T2	70318	13	0	0
T3	65405	11	0	0
T32	212741	29	0	0
T43	672065	26	0	0
T59	121008	14	0	0
T60	252084	31	0	0
T86	270527	53	0	0
T87	101342	19	0	0
T88	91974	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2845	2845	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483305282	48940	0	0
DepthKnown_A	483305282	483191945	0	0
RvalidKnown_A	483305282	483191945	0	0
WreadyKnown_A	483305282	483191945	0	0
gen_passthru_fifo.paramCheckPass	2845	2845	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	48940	0	0
T1	172602	22	0	0
T2	70318	12	0	0
T3	65405	10	0	0
T32	212741	25	0	0
T43	672065	5	0	0
T59	121008	13	0	0
T60	252084	24	0	0
T86	270527	52	0	0
T87	101342	18	0	0
T88	91974	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2845	2845	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483305282	48939	0	0
DepthKnown_A	483305282	483191945	0	0
RvalidKnown_A	483305282	483191945	0	0
WreadyKnown_A	483305282	483191945	0	0
gen_passthru_fifo.paramCheckPass	2845	2845	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	48939	0	0
T1	172602	22	0	0
T2	70318	12	0	0
T3	65405	10	0	0
T32	212741	25	0	0
T43	672065	5	0	0
T59	121008	13	0	0
T60	252084	24	0	0
T86	270527	52	0	0
T87	101342	18	0	0
T88	91974	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2845	2845	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483305282	36279	0	0
DepthKnown_A	483305282	483191945	0	0
RvalidKnown_A	483305282	483191945	0	0
WreadyKnown_A	483305282	483191945	0	0
gen_passthru_fifo.paramCheckPass	2845	2845	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	36279	0	0
T1	172602	3	0	0
T2	70318	1	0	0
T3	65405	1	0	0
T32	212741	4	0	0
T43	672065	21	0	0
T59	121008	1	0	0
T60	252084	7	0	0
T86	270527	1	0	0
T87	101342	1	0	0
T88	91974	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2845	2845	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483305282	38548	0	0
DepthKnown_A	483305282	483191945	0	0
RvalidKnown_A	483305282	483191945	0	0
WreadyKnown_A	483305282	483191945	0	0
gen_passthru_fifo.paramCheckPass	2845	2845	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	38548	0	0
T1	172602	3	0	0
T2	70318	1	0	0
T3	65405	1	0	0
T32	212741	4	0	0
T43	672065	21	0	0
T59	121008	1	0	0
T60	252084	7	0	0
T86	270527	1	0	0
T87	101342	1	0	0
T88	91974	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483305282	483191945	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2845	2845	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0