Unified Coverage Report :: Module :: sensor_ctrl_reg_top

Module : sensor_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.49	100.00	77.97			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg	94.49	100.00	77.97			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.49	100.00	77.97			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.48	90.61	90.26			93.06	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.69	90.41	79.66	93.39		100.00	100.00	u_sensor_ctrl_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_alert	100.00	100.00
u_alert_test_recov_alert	100.00	100.00
u_alert_trig_val_0	100.00	100.00	100.00			100.00
u_alert_trig_val_1	100.00	100.00	100.00			100.00
u_alert_trig_val_10	100.00	100.00	100.00			100.00
u_alert_trig_val_2	100.00	100.00	100.00			100.00
u_alert_trig_val_3	100.00	100.00	100.00			100.00
u_alert_trig_val_4	100.00	100.00	100.00			100.00
u_alert_trig_val_5	100.00	100.00	100.00			100.00
u_alert_trig_val_6	100.00	100.00	100.00			100.00
u_alert_trig_val_7	100.00	100.00	100.00			100.00
u_alert_trig_val_8	100.00	100.00	100.00			100.00
u_alert_trig_val_9	100.00	100.00	100.00			100.00
u_cfg_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00					100.00
u_fatal_alert_en_val_0	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_1	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_10	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_2	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_3	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_4	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_5	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_6	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_7	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_8	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_9	96.30	88.89	100.00			100.00
u_fatal_alert_val_0	96.30	88.89	100.00			100.00
u_fatal_alert_val_1	47.78	33.33	50.00			60.00
u_fatal_alert_val_10	47.78	33.33	50.00			60.00
u_fatal_alert_val_11	96.30	88.89	100.00			100.00
u_fatal_alert_val_2	96.30	88.89	100.00			100.00
u_fatal_alert_val_3	96.30	88.89	100.00			100.00
u_fatal_alert_val_4	96.30	88.89	100.00			100.00
u_fatal_alert_val_5	47.78	33.33	50.00			60.00
u_fatal_alert_val_6	47.78	33.33	50.00			60.00
u_fatal_alert_val_7	47.78	33.33	50.00			60.00
u_fatal_alert_val_8	47.78	33.33	50.00			60.00
u_fatal_alert_val_9	47.78	33.33	50.00			60.00
u_intr_enable_init_status_change	100.00	100.00	100.00			100.00
u_intr_enable_io_status_change	100.00	100.00	100.00			100.00
u_intr_state_init_status_change	100.00	100.00	100.00			100.00
u_intr_state_io_status_change	100.00	100.00	100.00			100.00
u_intr_test_init_status_change	100.00	100.00
u_intr_test_io_status_change	100.00	100.00
u_prim_reg_we_check	100.00	100.00
u_recov_alert_val_0	100.00	100.00	100.00			100.00
u_recov_alert_val_1	100.00	100.00	100.00			100.00
u_recov_alert_val_10	100.00	100.00	100.00			100.00
u_recov_alert_val_2	100.00	100.00	100.00			100.00
u_recov_alert_val_3	100.00	100.00	100.00			100.00
u_recov_alert_val_4	100.00	100.00	100.00			100.00
u_recov_alert_val_5	100.00	100.00	100.00			100.00
u_recov_alert_val_6	100.00	100.00	100.00			100.00
u_recov_alert_val_7	100.00	100.00	100.00			100.00
u_recov_alert_val_8	100.00	100.00	100.00			100.00
u_recov_alert_val_9	100.00	100.00	100.00			100.00
u_reg_if	82.82	85.71	72.84			72.73	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_ast_init_done	62.59	77.78	50.00			60.00
u_status_io_pok	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		150	150	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	746	1	1	100.00
ALWAYS	1731	11	11	100.00
CONT_ASSIGN	1744	1	1	100.00
ALWAYS	1748	1	1	100.00
CONT_ASSIGN	1762	1	1	100.00
CONT_ASSIGN	1764	1	1	100.00
CONT_ASSIGN	1766	1	1	100.00
CONT_ASSIGN	1767	1	1	100.00
CONT_ASSIGN	1769	1	1	100.00
CONT_ASSIGN	1771	1	1	100.00
CONT_ASSIGN	1772	1	1	100.00
CONT_ASSIGN	1774	1	1	100.00
CONT_ASSIGN	1776	1	1	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1781	1	1	100.00
CONT_ASSIGN	1782	1	1	100.00
CONT_ASSIGN	1784	1	1	100.00
CONT_ASSIGN	1785	1	1	100.00
CONT_ASSIGN	1787	1	1	100.00
CONT_ASSIGN	1789	1	1	100.00
CONT_ASSIGN	1791	1	1	100.00
CONT_ASSIGN	1793	1	1	100.00
CONT_ASSIGN	1795	1	1	100.00
CONT_ASSIGN	1797	1	1	100.00
CONT_ASSIGN	1799	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1803	1	1	100.00
CONT_ASSIGN	1805	1	1	100.00
CONT_ASSIGN	1807	1	1	100.00
CONT_ASSIGN	1808	1	1	100.00
CONT_ASSIGN	1810	1	1	100.00
CONT_ASSIGN	1812	1	1	100.00
CONT_ASSIGN	1814	1	1	100.00
CONT_ASSIGN	1816	1	1	100.00
CONT_ASSIGN	1818	1	1	100.00
CONT_ASSIGN	1820	1	1	100.00
CONT_ASSIGN	1822	1	1	100.00
CONT_ASSIGN	1824	1	1	100.00
CONT_ASSIGN	1826	1	1	100.00
CONT_ASSIGN	1828	1	1	100.00
CONT_ASSIGN	1830	1	1	100.00
CONT_ASSIGN	1831	1	1	100.00
CONT_ASSIGN	1833	1	1	100.00
CONT_ASSIGN	1835	1	1	100.00
CONT_ASSIGN	1837	1	1	100.00
CONT_ASSIGN	1839	1	1	100.00
CONT_ASSIGN	1841	1	1	100.00
CONT_ASSIGN	1843	1	1	100.00
CONT_ASSIGN	1845	1	1	100.00
CONT_ASSIGN	1847	1	1	100.00
CONT_ASSIGN	1849	1	1	100.00
CONT_ASSIGN	1851	1	1	100.00
CONT_ASSIGN	1853	1	1	100.00
ALWAYS	1857	11	11	100.00
ALWAYS	1872	58	58	100.00
CONT_ASSIGN	1971	0	0
CONT_ASSIGN	1979	1	1	100.00
CONT_ASSIGN	1980	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
343	1	1
358	1	1
374	1	1
380	1	1
395	1	1
411	1	1
746	1	1
1731	1	1
1732	1	1
1733	1	1
1734	1	1
1735	1	1
1736	1	1
1737	1	1
1738	1	1
1739	1	1
1740	1	1
1741	1	1
1744	1	1
1748	1	1
1762	1	1
1764	1	1
1766	1	1
1767	1	1
1769	1	1
1771	1	1
1772	1	1
1774	1	1
1776	1	1
1777	1	1
1779	1	1
1781	1	1
1782	1	1
1784	1	1
1785	1	1
1787	1	1
1789	1	1
1791	1	1
1793	1	1
1795	1	1
1797	1	1
1799	1	1
1801	1	1
1803	1	1
1805	1	1
1807	1	1
1808	1	1
1810	1	1
1812	1	1
1814	1	1
1816	1	1
1818	1	1
1820	1	1
1822	1	1
1824	1	1
1826	1	1
1828	1	1
1830	1	1
1831	1	1
1833	1	1
1835	1	1
1837	1	1
1839	1	1
1841	1	1
1843	1	1
1845	1	1
1847	1	1
1849	1	1
1851	1	1
1853	1	1
1857	1	1
1858	1	1
1859	1	1
1860	1	1
1861	1	1
1862	1	1
1863	1	1
1864	1	1
1865	1	1
1866	1	1
1867	1	1
1872	1	1
1873	1	1
1875	1	1
1876	1	1
1880	1	1
1881	1	1
1885	1	1
1886	1	1
1890	1	1
1891	1	1
1895	1	1
1899	1	1
1900	1	1
1901	1	1
1902	1	1
1903	1	1
1904	1	1
1905	1	1
1906	1	1
1907	1	1
1908	1	1
1909	1	1
1913	1	1
1914	1	1
1915	1	1
1916	1	1
1917	1	1
1918	1	1
1919	1	1
1920	1	1
1921	1	1
1922	1	1
1923	1	1
1927	1	1
1928	1	1
1929	1	1
1930	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1941	1	1
1942	1	1
1943	1	1
1944	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1949	1	1
1950	1	1
1951	1	1
1952	1	1
1956	1	1
1957	1	1
1971		unreachable
1979	1	1
1980	1	1

---

Cond Coverage for Module : sensor_ctrl_reg_top

	Total	Covered	Percent
Conditions	118	92	77.97
Logical	118	92	77.97
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T117,T46

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T335
1	0	Not Covered

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T335
0	1	0	Not Covered
1	0	0	Covered	T335

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       746
 EXPRESSION (fatal_alert_en_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T198
1	1	Covered	T161,T162,T333

 LINE       1732
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1733
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1734
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1735
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1736
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_CFG_REGWEN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1737
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TRIG_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1738
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_EN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1739
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_RECOV_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1740
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1741
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_STATUS_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1744
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1744
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T117,T46
1	0	Covered	T1,T2,T3

 LINE       1748
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T117,T46
1	1	Not Covered

 LINE       1748
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	1	Not Covered
0	0	0	0	0	0	0	0	1	0	Covered	T29,T30,T31
0	0	0	0	0	0	0	1	0	0	Covered	T29,T30,T31
0	0	0	0	0	0	1	0	0	0	Covered	T29,T30,T31
0	0	0	0	0	1	0	0	0	0	Covered	T29,T30,T31
0	0	0	0	1	0	0	0	0	0	Not Covered
0	0	0	1	0	0	0	0	0	0	Not Covered
0	0	1	0	0	0	0	0	0	0	Not Covered
0	1	0	0	0	0	0	0	0	0	Not Covered
1	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3

 LINE       1748
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1748
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1748
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1748
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1748
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1748
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       1748
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       1748
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       1748
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       1748
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1762
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T117,T46
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T117,T118,T166

 LINE       1767
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T117,T46
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T117,T118,T166

 LINE       1772
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T117,T46
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T117,T118,T119

 LINE       1777
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T117,T46
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T62,T63,T226

 LINE       1782
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T117,T46
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T198

 LINE       1785
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T117,T46
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T16,T46,T104

 LINE       1808
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T117,T46
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T161,T162,T198

 LINE       1831
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T117,T46
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T16,T46,T163

---

Branch Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
TERNARY	1744	2	2	100.00
IF	68	3	3	100.00
CASE	1873	11	11	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1744	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T335
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1873	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : sensor_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	102103919	2347	0	0
reAfterRv	102103919	2347	0	0
rePulse	102103919	2051	0	0
wePulse	102103919	296	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	102103919	2347	0	0
T1	41805	1	0	0
T2	17255	1	0	0
T3	16076	1	0	0
T32	51819	2	0	0
T43	161686	2	0	0
T59	29422	1	0	0
T60	60883	1	0	0
T86	65309	1	0	0
T87	24701	1	0	0
T88	22453	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	102103919	2347	0	0
T1	41805	1	0	0
T2	17255	1	0	0
T3	16076	1	0	0
T32	51819	2	0	0
T43	161686	2	0	0
T59	29422	1	0	0
T60	60883	1	0	0
T86	65309	1	0	0
T87	24701	1	0	0
T88	22453	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	102103919	2051	0	0
T1	41805	1	0	0
T2	17255	1	0	0
T3	16076	1	0	0
T32	51819	2	0	0
T43	161686	2	0	0
T59	29422	1	0	0
T60	60883	1	0	0
T86	65309	1	0	0
T87	24701	1	0	0
T88	22453	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	102103919	296	0	0
T16	37642	3	0	0
T44	166590	0	0	0
T46	0	3	0	0
T62	0	2	0	0
T63	0	2	0	0
T67	54660	0	0	0
T68	59622	0	0	0
T104	0	3	0	0
T107	124886	0	0	0
T108	38143	0	0	0
T109	57123	0	0	0
T110	32222	0	0	0
T111	55632	0	0	0
T112	508024	0	0	0
T117	0	6	0	0
T161	0	21	0	0
T163	0	1	0	0
T226	0	2	0	0
T331	0	1	0	0