Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.79	96.47	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	823390894	3814	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	823390894	3814	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	3814	0	0
T1	172602	2	0	0
T2	70318	1	0	0
T3	65405	1	0	0
T32	212741	2	0	0
T43	672065	11	0	0
T59	121008	1	0	0
T60	252084	1	0	0
T85	472868	0	0	0
T86	270527	1	0	0
T87	101342	1	0	0
T88	91974	1	0	0
T145	73671	9	0	0
T146	0	4	0	0
T147	0	4	0	0
T274	0	4	0	0
T275	0	3	0	0
T276	0	11	0	0
T277	265793	0	0	0
T278	329643	0	0	0
T279	125431	0	0	0
T280	429096	0	0	0
T281	72297	0	0	0
T282	201705	0	0	0
T283	73079	0	0	0
T284	138235	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	3814	0	0
T1	172602	2	0	0
T2	70318	1	0	0
T3	65405	1	0	0
T32	212741	2	0	0
T43	672065	11	0	0
T59	121008	1	0	0
T60	252084	1	0	0
T85	472868	0	0	0
T86	270527	1	0	0
T87	101342	1	0	0
T88	91974	1	0	0
T145	73671	9	0	0
T146	0	4	0	0
T147	0	4	0	0
T274	0	4	0	0
T275	0	3	0	0
T276	0	11	0	0
T277	265793	0	0	0
T278	329643	0	0	0
T279	125431	0	0	0
T280	429096	0	0	0
T281	72297	0	0	0
T282	201705	0	0	0
T283	73079	0	0	0
T284	138235	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	411695447	35	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	411695447	35	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	35	0	0
T85	472868	0	0	0
T145	73671	9	0	0
T146	0	4	0	0
T147	0	4	0	0
T274	0	4	0	0
T275	0	3	0	0
T276	0	11	0	0
T277	265793	0	0	0
T278	329643	0	0	0
T279	125431	0	0	0
T280	429096	0	0	0
T281	72297	0	0	0
T282	201705	0	0	0
T283	73079	0	0	0
T284	138235	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	35	0	0
T85	472868	0	0	0
T145	73671	9	0	0
T146	0	4	0	0
T147	0	4	0	0
T274	0	4	0	0
T275	0	3	0	0
T276	0	11	0	0
T277	265793	0	0	0
T278	329643	0	0	0
T279	125431	0	0	0
T280	429096	0	0	0
T281	72297	0	0	0
T282	201705	0	0	0
T283	73079	0	0	0
T284	138235	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	411695447	3779	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	411695447	3779	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	3779	0	0
T1	172602	2	0	0
T2	70318	1	0	0
T3	65405	1	0	0
T32	212741	2	0	0
T43	672065	11	0	0
T59	121008	1	0	0
T60	252084	1	0	0
T86	270527	1	0	0
T87	101342	1	0	0
T88	91974	1	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	3779	0	0
T1	172602	2	0	0
T2	70318	1	0	0
T3	65405	1	0	0
T32	212741	2	0	0
T43	672065	11	0	0
T59	121008	1	0	0
T60	252084	1	0	0
T86	270527	1	0	0
T87	101342	1	0	0
T88	91974	1	0	0