Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T146,T147,T274
0	1	Covered	T146,T147,T274
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T146,T147,T274
1	Covered	T146,T147,T274

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T146,T147,T274
1	Covered	T146,T147,T274

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T146,T147,T274
1	1	Covered	T146,T147,T274

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T146,T147,T274
1	0	Covered	T146,T147,T274
1	1	Covered	T146,T147,T274

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T146,T147,T274

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T146,T147,T274
0	Covered	T146,T147,T274

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T146,T147,T274
0	Covered	T146,T147,T274

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	823390894	805066094	0	0
CheckNGreaterZero_A	1908	1908	0	0
GntImpliesReady_A	823390894	5350	0	0
GntImpliesValid_A	823390894	5350	0	0
GrantKnown_A	823390894	805066094	0	0
IdxKnown_A	823390894	805066094	0	0
IndexIsCorrect_A	823390894	5350	0	0
NoReadyValidNoGrant_A	823390894	0	0	0
Priority_A	823390894	5350	0	0
ReadyAndValidImplyGrant_A	823390894	5350	0	0
ReqAndReadyImplyGrant_A	823390894	5350	0	0
ReqImpliesValid_A	823390894	5350	0	0
ValidKnown_A	823390894	805066094	0	0
gen_data_port_assertion.DataFlow_A	823390894	5350	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	805066094	0	0
T1	345204	345102	0	0
T2	140636	140512	0	0
T3	130810	130686	0	0
T32	425482	425262	0	0
T43	1344130	1344014	0	0
T59	242016	241914	0	0
T60	504168	504058	0	0
T86	541054	540944	0	0
T87	202684	202560	0	0
T88	183948	183838	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1908	1908	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T32	2	2	0	0
T43	2	2	0	0
T59	2	2	0	0
T60	2	2	0	0
T86	2	2	0	0
T87	2	2	0	0
T88	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	5350	0	0
T91	552704	0	0	0
T146	142642	1786	0	0
T147	0	1781	0	0
T274	0	1783	0	0
T360	528542	0	0	0
T361	291394	0	0	0
T362	311782	0	0	0
T363	385020	0	0	0
T364	1359534	0	0	0
T365	254476	0	0	0
T366	320340	0	0	0
T367	355946	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	5350	0	0
T91	552704	0	0	0
T146	142642	1786	0	0
T147	0	1781	0	0
T274	0	1783	0	0
T360	528542	0	0	0
T361	291394	0	0	0
T362	311782	0	0	0
T363	385020	0	0	0
T364	1359534	0	0	0
T365	254476	0	0	0
T366	320340	0	0	0
T367	355946	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	805066094	0	0
T1	345204	345102	0	0
T2	140636	140512	0	0
T3	130810	130686	0	0
T32	425482	425262	0	0
T43	1344130	1344014	0	0
T59	242016	241914	0	0
T60	504168	504058	0	0
T86	541054	540944	0	0
T87	202684	202560	0	0
T88	183948	183838	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	805066094	0	0
T1	345204	345102	0	0
T2	140636	140512	0	0
T3	130810	130686	0	0
T32	425482	425262	0	0
T43	1344130	1344014	0	0
T59	242016	241914	0	0
T60	504168	504058	0	0
T86	541054	540944	0	0
T87	202684	202560	0	0
T88	183948	183838	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	5350	0	0
T91	552704	0	0	0
T146	142642	1786	0	0
T147	0	1781	0	0
T274	0	1783	0	0
T360	528542	0	0	0
T361	291394	0	0	0
T362	311782	0	0	0
T363	385020	0	0	0
T364	1359534	0	0	0
T365	254476	0	0	0
T366	320340	0	0	0
T367	355946	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	5350	0	0
T91	552704	0	0	0
T146	142642	1786	0	0
T147	0	1781	0	0
T274	0	1783	0	0
T360	528542	0	0	0
T361	291394	0	0	0
T362	311782	0	0	0
T363	385020	0	0	0
T364	1359534	0	0	0
T365	254476	0	0	0
T366	320340	0	0	0
T367	355946	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	5350	0	0
T91	552704	0	0	0
T146	142642	1786	0	0
T147	0	1781	0	0
T274	0	1783	0	0
T360	528542	0	0	0
T361	291394	0	0	0
T362	311782	0	0	0
T363	385020	0	0	0
T364	1359534	0	0	0
T365	254476	0	0	0
T366	320340	0	0	0
T367	355946	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	5350	0	0
T91	552704	0	0	0
T146	142642	1786	0	0
T147	0	1781	0	0
T274	0	1783	0	0
T360	528542	0	0	0
T361	291394	0	0	0
T362	311782	0	0	0
T363	385020	0	0	0
T364	1359534	0	0	0
T365	254476	0	0	0
T366	320340	0	0	0
T367	355946	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	5350	0	0
T91	552704	0	0	0
T146	142642	1786	0	0
T147	0	1781	0	0
T274	0	1783	0	0
T360	528542	0	0	0
T361	291394	0	0	0
T362	311782	0	0	0
T363	385020	0	0	0
T364	1359534	0	0	0
T365	254476	0	0	0
T366	320340	0	0	0
T367	355946	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	805066094	0	0
T1	345204	345102	0	0
T2	140636	140512	0	0
T3	130810	130686	0	0
T32	425482	425262	0	0
T43	1344130	1344014	0	0
T59	242016	241914	0	0
T60	504168	504058	0	0
T86	541054	540944	0	0
T87	202684	202560	0	0
T88	183948	183838	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	823390894	5350	0	0
T91	552704	0	0	0
T146	142642	1786	0	0
T147	0	1781	0	0
T274	0	1783	0	0
T360	528542	0	0	0
T361	291394	0	0	0
T362	311782	0	0	0
T363	385020	0	0	0
T364	1359534	0	0	0
T365	254476	0	0	0
T366	320340	0	0	0
T367	355946	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T146,T147,T274
0	1	Covered	T146,T147,T274
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T146,T147,T274
1	Covered	T146,T147,T274

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T146,T147,T274
1	Covered	T146,T147,T274

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T146,T147,T274
1	1	Covered	T146,T147,T274

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T146,T147,T274
1	0	Covered	T146,T147,T274
1	1	Covered	T146,T147,T274

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T146,T147,T274

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T146,T147,T274
0	Covered	T146,T147,T274

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T146,T147,T274
0	Covered	T146,T147,T274

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411695447	402533047	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	411695447	4318	0	0
GntImpliesValid_A	411695447	4318	0	0
GrantKnown_A	411695447	402533047	0	0
IdxKnown_A	411695447	402533047	0	0
IndexIsCorrect_A	411695447	4318	0	0
NoReadyValidNoGrant_A	411695447	0	0	0
Priority_A	411695447	4318	0	0
ReadyAndValidImplyGrant_A	411695447	4318	0	0
ReqAndReadyImplyGrant_A	411695447	4318	0	0
ReqImpliesValid_A	411695447	4318	0	0
ValidKnown_A	411695447	402533047	0	0
gen_data_port_assertion.DataFlow_A	411695447	4318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	402533047	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	4318	0	0
T91	276352	0	0	0
T146	71321	1442	0	0
T147	0	1437	0	0
T274	0	1439	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	4318	0	0
T91	276352	0	0	0
T146	71321	1442	0	0
T147	0	1437	0	0
T274	0	1439	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	402533047	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	402533047	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	4318	0	0
T91	276352	0	0	0
T146	71321	1442	0	0
T147	0	1437	0	0
T274	0	1439	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	4318	0	0
T91	276352	0	0	0
T146	71321	1442	0	0
T147	0	1437	0	0
T274	0	1439	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	4318	0	0
T91	276352	0	0	0
T146	71321	1442	0	0
T147	0	1437	0	0
T274	0	1439	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	4318	0	0
T91	276352	0	0	0
T146	71321	1442	0	0
T147	0	1437	0	0
T274	0	1439	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	4318	0	0
T91	276352	0	0	0
T146	71321	1442	0	0
T147	0	1437	0	0
T274	0	1439	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	402533047	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	4318	0	0
T91	276352	0	0	0
T146	71321	1442	0	0
T147	0	1437	0	0
T274	0	1439	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T146,T147,T274
0	1	Covered	T146,T147,T274
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T146,T147,T274
1	Covered	T146,T147,T274

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T146,T147,T274
1	Covered	T146,T147,T274

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T146,T147,T274
1	1	Covered	T146,T147,T274

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T146,T147,T274
1	0	Covered	T146,T147,T274
1	1	Covered	T146,T147,T274

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T146,T147,T274

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T146,T147,T274
0	Covered	T146,T147,T274

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T146,T147,T274
0	Covered	T146,T147,T274

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	411695447	402533047	0	0
CheckNGreaterZero_A	954	954	0	0
GntImpliesReady_A	411695447	1032	0	0
GntImpliesValid_A	411695447	1032	0	0
GrantKnown_A	411695447	402533047	0	0
IdxKnown_A	411695447	402533047	0	0
IndexIsCorrect_A	411695447	1032	0	0
NoReadyValidNoGrant_A	411695447	0	0	0
Priority_A	411695447	1032	0	0
ReadyAndValidImplyGrant_A	411695447	1032	0	0
ReqAndReadyImplyGrant_A	411695447	1032	0	0
ReqImpliesValid_A	411695447	1032	0	0
ValidKnown_A	411695447	402533047	0	0
gen_data_port_assertion.DataFlow_A	411695447	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	402533047	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	954	954	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	1032	0	0
T91	276352	0	0	0
T146	71321	344	0	0
T147	0	344	0	0
T274	0	344	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	1032	0	0
T91	276352	0	0	0
T146	71321	344	0	0
T147	0	344	0	0
T274	0	344	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	402533047	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	402533047	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	1032	0	0
T91	276352	0	0	0
T146	71321	344	0	0
T147	0	344	0	0
T274	0	344	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	1032	0	0
T91	276352	0	0	0
T146	71321	344	0	0
T147	0	344	0	0
T274	0	344	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	1032	0	0
T91	276352	0	0	0
T146	71321	344	0	0
T147	0	344	0	0
T274	0	344	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	1032	0	0
T91	276352	0	0	0
T146	71321	344	0	0
T147	0	344	0	0
T274	0	344	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	1032	0	0
T91	276352	0	0	0
T146	71321	344	0	0
T147	0	344	0	0
T274	0	344	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	402533047	0	0
T1	172602	172551	0	0
T2	70318	70256	0	0
T3	65405	65343	0	0
T32	212741	212631	0	0
T43	672065	672007	0	0
T59	121008	120957	0	0
T60	252084	252029	0	0
T86	270527	270472	0	0
T87	101342	101280	0	0
T88	91974	91919	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411695447	1032	0	0
T91	276352	0	0	0
T146	71321	344	0	0
T147	0	344	0	0
T274	0	344	0	0
T360	264271	0	0	0
T361	145697	0	0	0
T362	155891	0	0	0
T363	192510	0	0	0
T364	679767	0	0	0
T365	127238	0	0	0
T366	160170	0	0	0
T367	177973	0	0	0