Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3748376	1			T75	1488		T76	258		T79	82
values[2]	761358	1			T75	375		T76	548		T79	42
values[3]	109269	1			T75	1		T76	497		T107	32
values[4]	57759	1			T76	335		T107	5		T532	16
values[5]	39100	1			T76	141		T532	10		T522	102
values[6]	29696	1			T76	85		T532	13		T522	84
values[7]	23876	1			T76	36		T532	8		T522	56
values[8]	20058	1			T76	22		T532	1		T522	51
values[9]	17572	1			T76	23		T522	33		T430	14
values[10]	16254	1			T76	19		T522	22		T430	14
values[11]	15191	1			T76	16		T522	30		T430	15
values[12]	14197	1			T76	12		T522	13		T430	14
values[13]	13476	1			T76	8		T522	9		T430	14
values[14]	12882	1			T76	6		T522	7		T430	14
values[15]	12381	1			T76	1		T522	4		T430	14
values[16]	12142	1			T76	1		T522	3		T430	14
values[17]	11556	1			T76	1		T522	4		T430	14
values[18]	11161	1			T76	1		T522	5		T430	14
values[19]	10713	1			T76	2		T522	4		T430	14
values[20]	10036	1			T76	2		T522	2		T430	14
values[21]	10129	1			T76	1		T522	2		T430	14
values[22]	9634	1			T76	2		T522	4		T430	14
values[23]	9325	1			T76	2		T522	4		T430	14
values[24]	9261	1			T76	1		T522	2		T430	14
values[25]	8958	1			T76	1		T522	5		T430	14
values[26]	8578	1			T76	1		T522	10		T430	14
values[27]	8251	1			T76	2		T522	13		T430	15
values[28]	7629	1			T76	2		T522	6		T430	14
values[29]	7194	1			T76	2		T522	5		T430	15
values[30]	6736	1			T76	1		T522	2		T430	14
values[31]	6244	1			T76	2		T522	3		T430	14
values[32]	5834	1			T76	2		T522	3		T430	14
values[33]	5366	1			T76	1		T522	2		T430	14
values[34]	5008	1			T76	1		T522	2		T430	14
values[35]	4648	1			T76	1		T522	8		T430	14
values[36]	4303	1			T76	1		T522	4		T430	14
values[37]	4079	1			T76	2		T522	4		T430	15
values[38]	3948	1			T76	3		T522	1		T430	14
values[39]	3665	1			T76	1		T522	2		T430	14
values[40]	3471	1			T76	1		T522	3		T430	14
values[41]	3418	1			T76	2		T522	1		T430	14
values[42]	3387	1			T76	1		T522	2		T430	14
values[43]	3282	1			T76	1		T522	1		T430	14
values[44]	3161	1			T76	1		T522	1		T430	14
values[45]	3245	1			T76	3		T430	15		T520	5
values[46]	3220	1			T76	4		T430	14		T520	8
values[47]	3099	1			T76	1		T430	14		T520	3
values[48]	2967	1			T76	2		T430	14		T520	9
values[49]	2940	1			T76	1		T430	14		T520	2
values[50]	2894	1			T76	3		T430	14		T520	9
values[51]	2890	1			T76	6		T430	14		T520	3
values[52]	2686	1			T76	4		T430	14		T520	13
values[53]	2728	1			T76	1		T430	15		T521	10
values[54]	2617	1			T76	1		T430	14		T521	10
values[55]	2688	1			T76	2		T430	14		T521	11
values[56]	2570	1			T76	2		T430	14		T521	10
values[57]	2548	1			T76	2		T430	14		T521	10
values[58]	2526	1			T76	2		T430	14		T521	10
values[59]	2476	1			T76	2		T430	14		T521	10
values[60]	2515	1			T76	2		T430	15		T521	10
values[61]	2722	1			T76	2		T430	14		T521	10
values[62]	4306	1			T76	4		T430	14		T521	10
values[63]	15580	1			T76	12		T430	170		T521	12
values[64]	214639	1			T76	93		T430	2313		T521	1854

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4830331	1			T75	1473		T76	1505		T79	97
values[2]	806695	1			T75	435		T76	403		T79	21
values[3]	72887	1			T75	14		T76	121		T107	13
values[4]	12793	1			T76	64		T107	3		T80	1
values[5]	4862	1			T76	44		T428	1		T430	19
values[6]	3141	1			T76	30		T430	6		T433	12
values[7]	2601	1			T76	9		T430	4		T433	2
values[8]	2011	1			T76	9		T430	1		T819	1
values[9]	1657	1			T430	1		T819	1		T519	2
values[10]	1583	1			T430	1		T819	1		T519	1
values[11]	1463	1			T430	1		T819	3		T519	1
values[12]	1389	1			T430	1		T819	3		T519	2
values[13]	1321	1			T430	1		T819	2		T519	1
values[14]	1186	1			T430	1		T819	2		T519	1
values[15]	1083	1			T430	1		T819	1		T519	1
values[16]	924	1			T430	1		T819	4		T519	2
values[17]	894	1			T430	1		T819	2		T519	3
values[18]	856	1			T430	1		T819	6		T519	1
values[19]	848	1			T430	1		T819	1		T519	4
values[20]	880	1			T430	1		T819	2		T519	1
values[21]	800	1			T430	1		T819	3		T519	1
values[22]	756	1			T430	1		T819	1		T519	2
values[23]	749	1			T430	1		T819	1		T519	1
values[24]	711	1			T430	1		T819	1		T519	1
values[25]	598	1			T430	1		T819	1		T519	1
values[26]	570	1			T430	1		T819	1		T519	2
values[27]	540	1			T430	1		T819	2		T519	1
values[28]	547	1			T430	1		T819	1		T519	1
values[29]	515	1			T430	1		T819	2		T519	1
values[30]	546	1			T430	1		T819	1		T519	2
values[31]	499	1			T430	1		T819	1		T519	1
values[32]	494	1			T430	1		T819	1		T519	1
values[33]	502	1			T430	1		T819	1		T519	1
values[34]	450	1			T430	1		T819	1		T519	1
values[35]	478	1			T430	1		T819	2		T519	2
values[36]	513	1			T430	1		T819	2		T519	1
values[37]	507	1			T430	1		T819	2		T519	4
values[38]	447	1			T430	1		T819	1		T519	5
values[39]	471	1			T430	1		T819	1		T519	3
values[40]	468	1			T430	1		T819	1		T519	4
values[41]	441	1			T430	1		T819	1		T519	2
values[42]	393	1			T430	1		T819	1		T519	1
values[43]	361	1			T430	1		T819	1		T519	3
values[44]	375	1			T430	1		T819	2		T519	1
values[45]	364	1			T430	1		T819	5		T519	1
values[46]	362	1			T430	1		T819	1		T519	2
values[47]	358	1			T430	1		T819	2		T519	3
values[48]	359	1			T430	1		T819	2		T519	1
values[49]	339	1			T430	1		T819	1		T519	2
values[50]	333	1			T430	1		T819	3		T519	2
values[51]	366	1			T430	1		T819	3		T519	2
values[52]	329	1			T430	1		T819	1		T519	3
values[53]	339	1			T430	1		T819	1		T519	2
values[54]	353	1			T430	2		T819	1		T519	1
values[55]	346	1			T430	1		T819	1		T519	1
values[56]	367	1			T430	1		T819	1		T519	1
values[57]	321	1			T430	1		T819	1		T519	1
values[58]	330	1			T430	1		T819	1		T519	1
values[59]	341	1			T430	1		T819	1		T519	2
values[60]	331	1			T430	1		T819	1		T519	1
values[61]	398	1			T430	1		T819	2		T519	1
values[62]	724	1			T430	1		T819	4		T519	5
values[63]	2949	1			T430	2		T819	13		T519	23
values[64]	24121	1			T430	207		T819	174		T519	84

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	566728	1			T75	13		T76	10		T79	1
values[2]	2699876	1			T75	1412		T76	124		T79	120
values[3]	1153923	1			T75	399		T76	560		T79	40
values[4]	150630	1			T75	1		T76	481		T107	37
values[5]	77356	1			T76	317		T107	7		T427	7
values[6]	50887	1			T76	208		T107	1		T427	3
values[7]	37540	1			T76	123		T427	2		T522	133
values[8]	29878	1			T76	110		T427	1		T522	105
values[9]	25822	1			T76	63		T522	96		T430	15
values[10]	22914	1			T76	40		T522	73		T430	14
values[11]	20163	1			T76	37		T522	58		T430	15
values[12]	18611	1			T76	16		T522	53		T430	14
values[13]	17759	1			T76	6		T522	32		T430	14
values[14]	16210	1			T76	7		T522	14		T430	14
values[15]	15441	1			T76	8		T522	3		T430	14
values[16]	14695	1			T76	17		T522	10		T430	14
values[17]	13889	1			T76	5		T522	7		T430	14
values[18]	13353	1			T76	6		T522	7		T430	14
values[19]	12871	1			T76	3		T522	5		T430	14
values[20]	12807	1			T76	3		T522	11		T430	14
values[21]	12100	1			T76	4		T522	3		T430	14
values[22]	11994	1			T76	1		T522	3		T430	14
values[23]	11151	1			T76	3		T522	8		T430	14
values[24]	10702	1			T76	2		T522	8		T430	14
values[25]	10171	1			T76	2		T522	6		T430	14
values[26]	9966	1			T76	4		T522	4		T430	14
values[27]	9698	1			T76	5		T522	2		T430	14
values[28]	8852	1			T76	2		T522	1		T430	14
values[29]	8052	1			T76	1		T522	4		T430	14
values[30]	7542	1			T76	3		T522	2		T430	14
values[31]	7027	1			T76	7		T522	2		T430	15
values[32]	6364	1			T76	10		T522	1		T430	14
values[33]	5871	1			T76	9		T522	2		T430	14
values[34]	5444	1			T76	4		T522	6		T430	14
values[35]	5126	1			T76	4		T522	10		T430	14
values[36]	4923	1			T76	2		T522	11		T430	14
values[37]	4631	1			T76	1		T522	9		T430	14
values[38]	4306	1			T76	2		T522	10		T430	14
values[39]	4013	1			T76	1		T522	3		T430	15
values[40]	3834	1			T76	2		T522	2		T430	14
values[41]	3771	1			T76	3		T522	1		T430	15
values[42]	3647	1			T76	1		T522	1		T430	14
values[43]	3689	1			T76	3		T522	4		T430	14
values[44]	3725	1			T76	1		T522	15		T430	14
values[45]	3583	1			T76	3		T522	5		T430	14
values[46]	3388	1			T76	7		T522	2		T430	14
values[47]	3292	1			T76	1		T522	7		T430	14
values[48]	3286	1			T76	2		T522	10		T430	14
values[49]	3302	1			T76	1		T522	10		T430	15
values[50]	3282	1			T76	1		T522	4		T430	14
values[51]	3137	1			T76	2		T522	7		T430	14
values[52]	3108	1			T76	3		T522	1		T430	14
values[53]	2998	1			T76	3		T430	14		T521	11
values[54]	3013	1			T76	1		T430	14		T521	10
values[55]	2908	1			T76	1		T430	14		T521	10
values[56]	2880	1			T76	1		T430	14		T521	10
values[57]	2878	1			T76	1		T430	14		T521	11
values[58]	2794	1			T76	7		T430	14		T521	10
values[59]	2739	1			T76	8		T430	14		T521	11
values[60]	2705	1			T76	6		T430	14		T521	11
values[61]	2826	1			T76	10		T430	14		T521	10
values[62]	3956	1			T76	3		T430	15		T521	10
values[63]	19474	1			T76	6		T430	16		T521	249
values[64]	202160	1			T76	55		T430	2338		T521	1710