Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2183646	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25184355

1

T1

5284

T2

32455

T3

9517

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17885934	1			T1	2142		T2	18578		T3	3058
values[0x0]	7873983	1			T1	3142		T2	13877		T3	6459
values[0x1]	1608084	1			T1	380		T2	1020		T3	411

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	672636	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26695365

1

T1

5664

T2

33475

T3

9928

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12475001	1			T1	2832		T2	16740		T3	4964
valid_sources[0x01]	12473521	1			T1	2832		T2	16735		T3	4964
valid_sources[0x02]	38079	1			T71	1		T207	2		T57	77
valid_sources[0x03]	38000	1			T71	2		T57	80		T171	3079
valid_sources[0x04]	38330	1			T71	1		T48	3		T412	2
valid_sources[0x05]	38739	1			T71	1		T207	1		T57	60
valid_sources[0x06]	38683	1			T71	1		T57	77		T171	2935
valid_sources[0x07]	38546	1			T71	3		T412	3		T207	1
valid_sources[0x08]	39250	1			T412	1		T207	1		T57	77
valid_sources[0x09]	39574	1			T57	85		T171	2905		T359	2921
valid_sources[0x0a]	38429	1			T71	1		T78	4		T57	78
valid_sources[0x0b]	41186	1			T71	1		T412	1		T207	2
valid_sources[0x0c]	39600	1			T48	4		T412	1		T207	1
valid_sources[0x0d]	38428	1			T71	1		T78	12		T57	84
valid_sources[0x0e]	38805	1			T57	74		T171	3187		T359	3001
valid_sources[0x0f]	38291	1			T207	1		T57	66		T171	3046
valid_sources[0x10]	38248	1			T48	1		T412	2		T57	62
valid_sources[0x11]	38689	1			T412	3		T57	65		T171	2923
valid_sources[0x12]	38716	1			T71	1		T45	12		T207	2
valid_sources[0x13]	39040	1			T71	1		T57	63		T171	3124
valid_sources[0x14]	38208	1			T412	3		T57	82		T171	2976
valid_sources[0x15]	38876	1			T48	2		T207	1		T57	62
valid_sources[0x16]	38107	1			T57	84		T171	3133		T359	3021
valid_sources[0x17]	39710	1			T71	2		T78	2		T207	3
valid_sources[0x18]	39263	1			T78	4		T48	2		T412	1
valid_sources[0x19]	39046	1			T71	1		T45	2		T48	4
valid_sources[0x1a]	39164	1			T412	3		T57	75		T171	3181
valid_sources[0x1b]	39550	1			T207	1		T57	76		T171	2965
valid_sources[0x1c]	38340	1			T71	2		T78	3		T57	89
valid_sources[0x1d]	39098	1			T207	2		T57	86		T171	3064
valid_sources[0x1e]	39275	1			T71	1		T48	8		T207	1
valid_sources[0x1f]	38298	1			T71	3		T207	1		T57	63
valid_sources[0x20]	39312	1			T71	1		T45	23		T207	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17111512

1

T1

2142

T2

18578

T3

3058

values[0x0]

all_enables

biggest_size

7835321

1

T1

3142

T2

13877

T3

6459

values[0x1]

all_enables

biggest_size

237522

1

T71

24

T78

16

T45

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2797214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

442495

1

T75

248

T76

321

T79

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1097569	1			T75	611		T76	678		T79	42
values[0x0]	1043929	1			T75	628		T76	776		T79	35
values[0x1]	1098211	1			T75	625		T76	744		T79	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2165285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1074424

1

T75

601

T76

727

T79

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51619	1			T75	56		T76	41		T107	3
valid_sources[0x01]	50066	1			T75	33		T76	39		T79	3
valid_sources[0x02]	50667	1			T75	28		T76	17		T80	1
valid_sources[0x03]	51065	1			T75	13		T76	57		T79	2
valid_sources[0x04]	50749	1			T75	9		T76	30		T107	7
valid_sources[0x05]	50640	1			T75	13		T76	51		T79	1
valid_sources[0x06]	50007	1			T75	21		T76	21		T80	3
valid_sources[0x07]	49934	1			T75	58		T76	16		T80	2
valid_sources[0x08]	50989	1			T75	19		T76	50		T79	4
valid_sources[0x09]	50056	1			T75	12		T76	33		T107	1
valid_sources[0x0a]	50187	1			T75	14		T76	36		T107	6
valid_sources[0x0b]	50544	1			T75	24		T76	26		T80	3
valid_sources[0x0c]	51239	1			T75	43		T76	44		T107	3
valid_sources[0x0d]	50043	1			T75	1		T76	43		T80	1
valid_sources[0x0e]	51482	1			T75	2		T76	47		T79	10
valid_sources[0x0f]	51086	1			T75	24		T76	30		T241	1
valid_sources[0x10]	50898	1			T75	4		T76	25		T241	1
valid_sources[0x11]	50049	1			T75	52		T76	24		T107	1
valid_sources[0x12]	49321	1			T75	21		T76	21		T79	3
valid_sources[0x13]	50705	1			T75	27		T76	57		T241	2
valid_sources[0x14]	50420	1			T75	25		T76	29		T107	11
valid_sources[0x15]	50977	1			T75	30		T76	15		T79	1
valid_sources[0x16]	51529	1			T75	11		T76	31		T79	3
valid_sources[0x17]	49843	1			T75	40		T76	30		T107	2
valid_sources[0x18]	50708	1			T75	50		T76	27		T79	9
valid_sources[0x19]	49940	1			T75	21		T76	27		T107	6
valid_sources[0x1a]	50089	1			T75	16		T76	43		T80	1
valid_sources[0x1b]	49203	1			T75	61		T76	16		T79	2
valid_sources[0x1c]	49848	1			T75	29		T76	53		T241	2
valid_sources[0x1d]	50031	1			T75	6		T76	56		T79	2
valid_sources[0x1e]	50998	1			T75	51		T76	24		T80	3
valid_sources[0x1f]	50461	1			T75	27		T76	34		T107	1
valid_sources[0x20]	50569	1			T75	55		T76	26		T107	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46678

1

T75

19

T76

29

T79

2

values[0x0]

all_enables

biggest_size

349187

1

T75

206

T76

266

T79

6

values[0x1]

all_enables

biggest_size

46630

1

T75

23

T76

26

T79

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2977405	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

483646

1

T75

281

T76

318

T79

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1186623	1			T75	663		T76	724		T79	31
values[0x0]	1089694	1			T75	599		T76	723		T79	37
values[0x1]	1184734	1			T75	660		T76	738		T79	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2284582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1176469

1

T75

647

T76

758

T79

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54885	1			T75	34		T76	49		T107	2
valid_sources[0x01]	54153	1			T75	33		T76	15		T79	2
valid_sources[0x02]	54063	1			T75	22		T76	67		T107	1
valid_sources[0x03]	53851	1			T75	42		T76	37		T79	1
valid_sources[0x04]	53493	1			T75	35		T76	38		T79	2
valid_sources[0x05]	55388	1			T75	17		T76	21		T107	3
valid_sources[0x06]	54276	1			T75	38		T76	61		T79	1
valid_sources[0x07]	54080	1			T75	36		T76	44		T79	1
valid_sources[0x08]	54463	1			T75	27		T76	31		T79	1
valid_sources[0x09]	53523	1			T75	35		T76	30		T79	3
valid_sources[0x0a]	53122	1			T75	24		T76	2		T79	1
valid_sources[0x0b]	54350	1			T75	32		T76	35		T79	1
valid_sources[0x0c]	53645	1			T75	31		T76	23		T79	2
valid_sources[0x0d]	53375	1			T75	28		T76	17		T79	1
valid_sources[0x0e]	54068	1			T75	23		T76	43		T79	1
valid_sources[0x0f]	53723	1			T75	34		T76	34		T79	2
valid_sources[0x10]	55448	1			T75	28		T76	23		T79	2
valid_sources[0x11]	53509	1			T75	29		T76	17		T79	2
valid_sources[0x12]	54200	1			T75	35		T76	31		T79	1
valid_sources[0x13]	53223	1			T75	33		T76	23		T79	3
valid_sources[0x14]	54988	1			T75	30		T76	39		T79	2
valid_sources[0x15]	54269	1			T75	42		T76	16		T79	1
valid_sources[0x16]	54421	1			T75	26		T76	38		T79	1
valid_sources[0x17]	53474	1			T75	27		T76	53		T79	1
valid_sources[0x18]	54421	1			T75	28		T76	25		T79	4
valid_sources[0x19]	54657	1			T75	29		T76	37		T79	2
valid_sources[0x1a]	54808	1			T75	35		T76	23		T79	2
valid_sources[0x1b]	53235	1			T75	24		T76	38		T79	3
valid_sources[0x1c]	54477	1			T75	34		T76	24		T79	3
valid_sources[0x1d]	54166	1			T75	37		T76	19		T79	3
valid_sources[0x1e]	54746	1			T75	24		T76	47		T107	4
valid_sources[0x1f]	54636	1			T75	30		T76	41		T79	1
valid_sources[0x20]	54182	1			T75	23		T76	51		T79	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51327

1

T75

26

T76

27

T79

1

values[0x0]

all_enables

biggest_size

381219

1

T75

224

T76

255

T79

10

values[0x1]

all_enables

biggest_size

51100

1

T75

31

T76

36

T79

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2815953	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

444299

1

T75

280

T76

291

T79

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1105328	1			T75	589		T76	776		T79	68
values[0x0]	1049151	1			T75	616		T76	793		T79	48
values[0x1]	1105773	1			T75	620		T76	774		T79	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2180173	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1080079

1

T75

648

T76

735

T79

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50954	1			T75	29		T76	34		T107	2
valid_sources[0x01]	50660	1			T75	42		T76	43		T107	7
valid_sources[0x02]	50960	1			T75	30		T76	37		T107	4
valid_sources[0x03]	50499	1			T75	36		T76	39		T79	12
valid_sources[0x04]	51152	1			T75	15		T76	39		T79	6
valid_sources[0x05]	51147	1			T75	34		T76	38		T79	4
valid_sources[0x06]	51155	1			T75	19		T76	31		T79	2
valid_sources[0x07]	49369	1			T75	23		T76	30		T80	1
valid_sources[0x08]	51608	1			T75	13		T76	40		T79	2
valid_sources[0x09]	50947	1			T75	21		T76	32		T80	1
valid_sources[0x0a]	50136	1			T75	36		T76	27		T80	1
valid_sources[0x0b]	51089	1			T75	35		T76	37		T241	3
valid_sources[0x0c]	51222	1			T75	19		T76	29		T107	2
valid_sources[0x0d]	50907	1			T75	40		T76	44		T79	2
valid_sources[0x0e]	51475	1			T75	44		T76	30		T107	2
valid_sources[0x0f]	51032	1			T75	10		T76	37		T80	2
valid_sources[0x10]	50971	1			T75	21		T76	27		T79	3
valid_sources[0x11]	50095	1			T75	37		T76	32		T79	10
valid_sources[0x12]	51143	1			T75	33		T76	36		T107	6
valid_sources[0x13]	50141	1			T75	13		T76	34		T107	1
valid_sources[0x14]	51113	1			T75	43		T76	37		T107	4
valid_sources[0x15]	50887	1			T75	28		T76	33		T107	2
valid_sources[0x16]	50838	1			T75	29		T76	36		T107	5
valid_sources[0x17]	49861	1			T75	10		T76	36		T107	3
valid_sources[0x18]	50262	1			T75	28		T76	43		T157	2
valid_sources[0x19]	50779	1			T75	20		T76	32		T79	6
valid_sources[0x1a]	51670	1			T75	39		T76	37		T107	4
valid_sources[0x1b]	50816	1			T75	31		T76	37		T80	3
valid_sources[0x1c]	51276	1			T75	28		T76	25		T79	12
valid_sources[0x1d]	51579	1			T75	45		T76	37		T79	7
valid_sources[0x1e]	52474	1			T75	28		T76	49		T107	4
valid_sources[0x1f]	51296	1			T75	26		T76	37		T107	2
valid_sources[0x20]	50922	1			T75	55		T76	38		T107	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46988

1

T75

19

T76

29

T79

2

values[0x0]

all_enables

biggest_size

350298

1

T75

232

T76

233

T79

12

values[0x1]

all_enables

biggest_size

47013

1

T75

29

T76

29

T79

1