Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : pinmux
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.76 77.24 88.76 65.10 85.70 92.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon 92.84 98.99 88.76 98.76 85.70 92.00

Line Coverage for Module : pinmux
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TOTAL114788677.24
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WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
132 1 1
161 1 1
162 1 1
163 1 1
166 1 1
167 1 1
168 1 1
MISSING_ELSE
170 1 1
171 1 1
MISSING_ELSE
173 1 1
174 1 1
MISSING_ELSE
176 1 1
177 1 1
MISSING_ELSE
179 1 1
180 1 1
MISSING_ELSE
182 1 1
183 1 1
MISSING_ELSE
185 1 1
186 1 1
MISSING_ELSE
188 1 1
189 1 1
MISSING_ELSE
191 1 1
192 1 1
MISSING_ELSE
196 1 1
197 1 1
198 1 1
MISSING_ELSE
200 1 1
201 1 1
MISSING_ELSE
203 1 1
204 1 1
MISSING_ELSE
206 1 1
207 1 1
MISSING_ELSE
209 1 1
210 1 1
MISSING_ELSE
212 1 1
213 1 1
MISSING_ELSE
215 1 1
216 1 1
MISSING_ELSE
218 1 1
219 1 1
MISSING_ELSE
221 1 1
222 1 1
MISSING_ELSE
242 16 16
243 14 16
244 0 16
245 0 16
246 0 16
247 0 16
248 16 16
249 16 16
250 14 16
251 16 16
264 47 47
265 47 47
266 0 47
267 0 47
268 0 47
269 0 47
270 47 47
271 47 47
272 47 47
273 47 47
311 unreachable
312 1 1
410 1 1
413 1 1
414 1 1
415 1 1
416 1 1
417 1 1
418 1 1
420 1 1
423 1 1
424 1 1
425 1 1
426 1 1
MISSING_ELSE
431 1 1
432 1 1
433 1 1
434 1 1
MISSING_ELSE
450 1 1
454 57 57
464 1 1
465 1 1
469 47 47
473 47 47
482 47 47
486 47 47
491 47 47
493 47 47
501 1 1
505 16 16
509 16 16
518 16 16
522 16 16
527 16 16
529 16 16
541 1 1
546 1 1
551 8 8
572 3 8
576 1 1


Cond Coverage for Module : pinmux
TotalCoveredPercent
Conditions1975175388.76
Logical1975175388.76
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
132-48293.28
482-48686.43
48686.16
486-51891.10
522-55186.33

Toggle Coverage for Module : pinmux
TotalCoveredPercent
Totals 649 329 50.69
Total Bits 2940 1914 65.10
Total Bits 0->1 1470 958 65.17
Total Bits 1->0 1470 956 65.03

Ports 649 329 50.69
Port Bits 2940 1914 65.10
Port Bits 0->1 1470 958 65.17
Port Bits 1->0 1470 956 65.03

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
rst_sys_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
pin_wkup_req_o Yes Yes T14,T44,T50 Yes T42,T43,T14 OUTPUT
usb_wkup_req_o Yes Yes T56,T57,T58 Yes T59,T60,T61 OUTPUT
sleep_en_i Yes Yes T1,T2,T3 Yes T2,T51,T52 INPUT
strap_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
strap_en_override_i Unreachable Unreachable Unreachable INPUT
lc_dft_en_i[3:0] Yes Yes T3,T4,T29 Yes T1,T3,T51 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T3,T4,T29 Yes T1,T3,T51 INPUT
lc_check_byp_en_i[3:0] Yes Yes T4,T62,T63 Yes T4,T64,T62 INPUT
lc_escalate_en_i[3:0] Yes Yes T3,T65,T66 Yes T3,T65,T66 INPUT
pinmux_hw_debug_en_o[3:0] Yes Yes T3,T4,T65 Yes T1,T3,T51 OUTPUT
dft_strap_test_o.straps[1:0] No No Yes T67,T68,T69 OUTPUT
dft_strap_test_o.valid Yes Yes T3,T4,T65 Yes T1,T3,T51 OUTPUT
dft_hold_tap_sel_i Unreachable Unreachable Unreachable INPUT
lc_jtag_o.tdi Yes Yes T4,T64,T67 Yes T4,T64,T67 OUTPUT
lc_jtag_o.trst_n Yes Yes T4,T67,T62 Yes T4,T64,T70 OUTPUT
lc_jtag_o.tms Yes Yes T4,T64,T67 Yes T4,T64,T67 OUTPUT
lc_jtag_o.tck Yes Yes T4,T64,T67 Yes T4,T64,T70 OUTPUT
lc_jtag_i.tdo_oe Yes Yes T4,T64,T67 Yes T4,T64,T67 INPUT
lc_jtag_i.tdo Yes Yes T4,T64,T67 Yes T4,T64,T67 INPUT
rv_jtag_o.tdi Yes Yes T4,T29,T71 Yes T4,T29,T71 OUTPUT
rv_jtag_o.trst_n Yes Yes T4,T71,T68 Yes T4,T29,T71 OUTPUT
rv_jtag_o.tms Yes Yes T4,T29,T71 Yes T4,T29,T71 OUTPUT
rv_jtag_o.tck Yes Yes T4,T29,T71 Yes T4,T29,T71 OUTPUT
rv_jtag_i.tdo_oe Yes Yes T4,T29,T71 Yes T4,T29,T71 INPUT
rv_jtag_i.tdo Yes Yes T4,T29,T71 Yes T4,T29,T71 INPUT
dft_jtag_o.tdi Yes Yes T67,T68,T72 Yes T67,T68,T72 OUTPUT
dft_jtag_o.trst_n Yes Yes T67,T68,T72 Yes T67,T68,T72 OUTPUT
dft_jtag_o.tms Yes Yes T67,T68,T72 Yes T67,T68,T72 OUTPUT
dft_jtag_o.tck Yes Yes T67,T68,T72 Yes T67,T68,T72 OUTPUT
dft_jtag_i.tdo_oe Yes Yes T67,T73,T68 Yes T67,T73,T68 INPUT
dft_jtag_i.tdo Yes Yes T67,T73,T68 Yes T67,T73,T68 INPUT
usbdev_dppullup_en_i Yes Yes T17,T18,T22 Yes T16,T17,T18 INPUT
usbdev_dnpullup_en_i Yes Yes T17,T18,T56 Yes T17,T18,T56 INPUT
usb_dppullup_en_o Yes Yes T17,T18,T22 Yes T16,T17,T18 OUTPUT
usb_dnpullup_en_o Yes Yes T17,T18,T56 Yes T17,T18,T56 OUTPUT
usbdev_suspend_req_i Yes Yes T59,T60,T61 Yes T59,T60,T61 INPUT
usbdev_wake_ack_i Yes Yes T59,T60,T61 Yes T59,T60,T61 INPUT
usbdev_bus_reset_o Yes Yes T56 Yes T56 OUTPUT
usbdev_sense_lost_o Yes Yes T57,T58,T74 Yes T59,T60,T61 OUTPUT
usbdev_wake_detect_active_o Yes Yes T56,T57,T58 Yes T59,T60,T61 OUTPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[11:0] Yes Yes *T75,*T57,*T76 Yes T75,T57,T76 INPUT
tl_i.a_address[16:12] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[21:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T4,*T71,*T77 Yes T4,T71,T77 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T57,T76 Yes T75,T57,T76 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T71,T78,T45 Yes T71,T78,T45 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T75,T79,T80 Yes T75,T79,T80 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T75,T79,T80 Yes T75,T79,T80 OUTPUT
tl_o.d_source[5:0] Yes Yes *T45,*T48,*T75 Yes T45,T48,T75 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T57,T79 Yes T75,T57,T79 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
periph_to_mio_i[74:0] Yes Yes T12,T14,T23 Yes T12,T14,T23 INPUT
periph_to_mio_oe_i[74:0] Yes Yes T12,T24,T25 Yes T12,T14,T23 INPUT
mio_to_periph_o[56:0] Yes Yes T12,T14,T23 Yes T12,T14,T23 OUTPUT
periph_to_dio_i[11:0] Yes Yes *T15,*T16,*T17 Yes T16,T17,T18 INPUT
periph_to_dio_i[13:12] No No No INPUT
periph_to_dio_i[15:14] Yes Yes T9,T10,T11 Yes T9,T10,T11 INPUT
periph_to_dio_oe_i[15:0] Yes Yes T16,T17,T22 Yes T16,T17,T22 INPUT
dio_to_periph_o[15:0] Yes Yes T15,T16,T17 Yes T16,T17,T18 OUTPUT
mio_attr_o[0].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[0].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[0].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[0].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[0].keep_en No No No OUTPUT
mio_attr_o[0].schmitt_en No No No OUTPUT
mio_attr_o[0].od_en No No No OUTPUT
mio_attr_o[0].slew_rate[1:0] No No No OUTPUT
mio_attr_o[0].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[0].drive_strength[3:1] No No No OUTPUT
mio_attr_o[1].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[1].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[1].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[1].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[1].keep_en No No No OUTPUT
mio_attr_o[1].schmitt_en No No No OUTPUT
mio_attr_o[1].od_en No No No OUTPUT
mio_attr_o[1].slew_rate[1:0] No No No OUTPUT
mio_attr_o[1].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[1].drive_strength[3:1] No No No OUTPUT
mio_attr_o[2].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[2].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[2].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
mio_attr_o[2].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
mio_attr_o[2].keep_en No No No OUTPUT
mio_attr_o[2].schmitt_en No No No OUTPUT
mio_attr_o[2].od_en No No No OUTPUT
mio_attr_o[2].slew_rate[1:0] No No No OUTPUT
mio_attr_o[2].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[2].drive_strength[3:1] No No No OUTPUT
mio_attr_o[3].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[3].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[3].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[3].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[3].keep_en No No No OUTPUT
mio_attr_o[3].schmitt_en No No No OUTPUT
mio_attr_o[3].od_en No No No OUTPUT
mio_attr_o[3].slew_rate[1:0] No No No OUTPUT
mio_attr_o[3].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[3].drive_strength[3:1] No No No OUTPUT
mio_attr_o[4].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[4].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[4].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[4].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[4].keep_en No No No OUTPUT
mio_attr_o[4].schmitt_en No No No OUTPUT
mio_attr_o[4].od_en No No No OUTPUT
mio_attr_o[4].slew_rate[1:0] No No No OUTPUT
mio_attr_o[4].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[4].drive_strength[3:1] No No No OUTPUT
mio_attr_o[5].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[5].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[5].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[5].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[5].keep_en No No No OUTPUT
mio_attr_o[5].schmitt_en No No No OUTPUT
mio_attr_o[5].od_en No No No OUTPUT
mio_attr_o[5].slew_rate[1:0] No No No OUTPUT
mio_attr_o[5].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[5].drive_strength[3:1] No No No OUTPUT
mio_attr_o[6].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[6].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[6].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[6].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[6].keep_en No No No OUTPUT
mio_attr_o[6].schmitt_en No No No OUTPUT
mio_attr_o[6].od_en No No No OUTPUT
mio_attr_o[6].slew_rate[1:0] No No No OUTPUT
mio_attr_o[6].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[6].drive_strength[3:1] No No No OUTPUT
mio_attr_o[7].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[7].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[7].pull_en Yes Yes T26,T27,T28 Yes T33,T34,T35 OUTPUT
mio_attr_o[7].pull_select Yes Yes T26,T27,T28 Yes T33,T34,T35 OUTPUT
mio_attr_o[7].keep_en No No No OUTPUT
mio_attr_o[7].schmitt_en No No No OUTPUT
mio_attr_o[7].od_en No No No OUTPUT
mio_attr_o[7].slew_rate[1:0] No No No OUTPUT
mio_attr_o[7].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[7].drive_strength[3:1] No No No OUTPUT
mio_attr_o[8].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[8].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[8].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[8].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[8].keep_en No No No OUTPUT
mio_attr_o[8].schmitt_en No No No OUTPUT
mio_attr_o[8].od_en No No No OUTPUT
mio_attr_o[8].slew_rate[1:0] No No No OUTPUT
mio_attr_o[8].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[8].drive_strength[3:1] No No No OUTPUT
mio_attr_o[9].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[9].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[9].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
mio_attr_o[9].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
mio_attr_o[9].keep_en No No No OUTPUT
mio_attr_o[9].schmitt_en No No No OUTPUT
mio_attr_o[9].od_en No No No OUTPUT
mio_attr_o[9].slew_rate[1:0] No No No OUTPUT
mio_attr_o[9].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[9].drive_strength[3:1] No No No OUTPUT
mio_attr_o[10].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[10].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[10].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
mio_attr_o[10].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
mio_attr_o[10].keep_en No No No OUTPUT
mio_attr_o[10].schmitt_en No No No OUTPUT
mio_attr_o[10].od_en No No No OUTPUT
mio_attr_o[10].slew_rate[1:0] No No No OUTPUT
mio_attr_o[10].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[10].drive_strength[3:1] No No No OUTPUT
mio_attr_o[11].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[11].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[11].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[11].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[11].keep_en No No No OUTPUT
mio_attr_o[11].schmitt_en No No No OUTPUT
mio_attr_o[11].od_en No No No OUTPUT
mio_attr_o[11].slew_rate[1:0] No No No OUTPUT
mio_attr_o[11].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[11].drive_strength[3:1] No No No OUTPUT
mio_attr_o[12].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[12].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[12].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
mio_attr_o[12].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
mio_attr_o[12].keep_en No No No OUTPUT
mio_attr_o[12].schmitt_en No No No OUTPUT
mio_attr_o[12].od_en No No No OUTPUT
mio_attr_o[12].slew_rate[1:0] No No No OUTPUT
mio_attr_o[12].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[12].drive_strength[3:1] No No No OUTPUT
mio_attr_o[13].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[13].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[13].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
mio_attr_o[13].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
mio_attr_o[13].keep_en No No No OUTPUT
mio_attr_o[13].schmitt_en No No No OUTPUT
mio_attr_o[13].od_en No No No OUTPUT
mio_attr_o[13].slew_rate[1:0] No No No OUTPUT
mio_attr_o[13].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[13].drive_strength[3:1] No No No OUTPUT
mio_attr_o[14].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[14].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[14].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
mio_attr_o[14].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
mio_attr_o[14].keep_en No No No OUTPUT
mio_attr_o[14].schmitt_en No No No OUTPUT
mio_attr_o[14].od_en No No No OUTPUT
mio_attr_o[14].slew_rate[1:0] No No No OUTPUT
mio_attr_o[14].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[14].drive_strength[3:1] No No No OUTPUT
mio_attr_o[15].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[15].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[15].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
mio_attr_o[15].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
mio_attr_o[15].keep_en No No No OUTPUT
mio_attr_o[15].schmitt_en No No No OUTPUT
mio_attr_o[15].od_en No No No OUTPUT
mio_attr_o[15].slew_rate[1:0] No No No OUTPUT
mio_attr_o[15].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[15].drive_strength[3:1] No No No OUTPUT
mio_attr_o[16].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[16].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[16].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[16].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[16].keep_en No No No OUTPUT
mio_attr_o[16].schmitt_en No No No OUTPUT
mio_attr_o[16].od_en No No No OUTPUT
mio_attr_o[16].slew_rate[1:0] No No No OUTPUT
mio_attr_o[16].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[16].drive_strength[3:1] No No No OUTPUT
mio_attr_o[17].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[17].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[17].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[17].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[17].keep_en No No No OUTPUT
mio_attr_o[17].schmitt_en No No No OUTPUT
mio_attr_o[17].od_en No No No OUTPUT
mio_attr_o[17].slew_rate[1:0] No No No OUTPUT
mio_attr_o[17].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[17].drive_strength[3:1] No No No OUTPUT
mio_attr_o[18].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[18].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[18].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[18].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[18].keep_en No No No OUTPUT
mio_attr_o[18].schmitt_en No No No OUTPUT
mio_attr_o[18].od_en No No No OUTPUT
mio_attr_o[18].slew_rate[1:0] No No No OUTPUT
mio_attr_o[18].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[18].drive_strength[3:1] No No No OUTPUT
mio_attr_o[19].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[19].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[19].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[19].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[19].keep_en No No No OUTPUT
mio_attr_o[19].schmitt_en No No No OUTPUT
mio_attr_o[19].od_en No No No OUTPUT
mio_attr_o[19].slew_rate[1:0] No No No OUTPUT
mio_attr_o[19].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[19].drive_strength[3:1] No No No OUTPUT
mio_attr_o[20].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[20].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[20].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[20].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[20].keep_en No No No OUTPUT
mio_attr_o[20].schmitt_en No No No OUTPUT
mio_attr_o[20].od_en No No No OUTPUT
mio_attr_o[20].slew_rate[1:0] No No No OUTPUT
mio_attr_o[20].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[20].drive_strength[3:1] No No No OUTPUT
mio_attr_o[21].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[21].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[21].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[21].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[21].keep_en No No No OUTPUT
mio_attr_o[21].schmitt_en No No No OUTPUT
mio_attr_o[21].od_en No No No OUTPUT
mio_attr_o[21].slew_rate[1:0] No No No OUTPUT
mio_attr_o[21].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[21].drive_strength[3:1] No No No OUTPUT
mio_attr_o[22].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[22].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[22].pull_en Yes Yes T36,T37,T38 Yes T39,T4,T40 OUTPUT
mio_attr_o[22].pull_select Yes Yes T39,T41,T36 Yes T39,T41,T36 OUTPUT
mio_attr_o[22].keep_en No No No OUTPUT
mio_attr_o[22].schmitt_en No No No OUTPUT
mio_attr_o[22].od_en No No No OUTPUT
mio_attr_o[22].slew_rate[1:0] No No No OUTPUT
mio_attr_o[22].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[22].drive_strength[3:1] No No No OUTPUT
mio_attr_o[23].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[23].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[23].pull_en Yes Yes T36,T37,T38 Yes T39,T4,T40 OUTPUT
mio_attr_o[23].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[23].keep_en No No No OUTPUT
mio_attr_o[23].schmitt_en No No No OUTPUT
mio_attr_o[23].od_en No No No OUTPUT
mio_attr_o[23].slew_rate[1:0] No No No OUTPUT
mio_attr_o[23].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[23].drive_strength[3:1] No No No OUTPUT
mio_attr_o[24].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[24].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[24].pull_en Yes Yes T36,T37,T38 Yes T39,T4,T40 OUTPUT
mio_attr_o[24].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[24].keep_en No No No OUTPUT
mio_attr_o[24].schmitt_en No No No OUTPUT
mio_attr_o[24].od_en No No No OUTPUT
mio_attr_o[24].slew_rate[1:0] No No No OUTPUT
mio_attr_o[24].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[24].drive_strength[3:1] No No No OUTPUT
mio_attr_o[25].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[25].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[25].pull_en Yes Yes T2,T3,T29 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].pull_select Yes Yes T2,T3,T29 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].keep_en No No No OUTPUT
mio_attr_o[25].schmitt_en No No No OUTPUT
mio_attr_o[25].od_en No No No OUTPUT
mio_attr_o[25].slew_rate[1:0] No No No OUTPUT
mio_attr_o[25].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[25].drive_strength[3:1] No No No OUTPUT
mio_attr_o[26].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[26].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[26].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[26].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[26].keep_en No No No OUTPUT
mio_attr_o[26].schmitt_en No No No OUTPUT
mio_attr_o[26].od_en No No No OUTPUT
mio_attr_o[26].slew_rate[1:0] No No No OUTPUT
mio_attr_o[26].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[26].drive_strength[3:1] No No No OUTPUT
mio_attr_o[27].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[27].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[27].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[27].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[27].keep_en No No No OUTPUT
mio_attr_o[27].schmitt_en No No No OUTPUT
mio_attr_o[27].od_en No No No OUTPUT
mio_attr_o[27].slew_rate[1:0] No No No OUTPUT
mio_attr_o[27].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[27].drive_strength[3:1] No No No OUTPUT
mio_attr_o[28].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[28].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[28].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[28].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[28].keep_en No No No OUTPUT
mio_attr_o[28].schmitt_en No No No OUTPUT
mio_attr_o[28].od_en No No No OUTPUT
mio_attr_o[28].slew_rate[1:0] No No No OUTPUT
mio_attr_o[28].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[28].drive_strength[3:1] No No No OUTPUT
mio_attr_o[29].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[29].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[29].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[29].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[29].keep_en No No No OUTPUT
mio_attr_o[29].schmitt_en No No No OUTPUT
mio_attr_o[29].od_en No No No OUTPUT
mio_attr_o[29].slew_rate[1:0] No No No OUTPUT
mio_attr_o[29].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[29].drive_strength[3:1] No No No OUTPUT
mio_attr_o[30].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[30].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[30].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[30].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[30].keep_en No No No OUTPUT
mio_attr_o[30].schmitt_en No No No OUTPUT
mio_attr_o[30].od_en No No No OUTPUT
mio_attr_o[30].slew_rate[1:0] No No No OUTPUT
mio_attr_o[30].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[30].drive_strength[3:1] No No No OUTPUT
mio_attr_o[31].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[31].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[31].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[31].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[31].keep_en No No No OUTPUT
mio_attr_o[31].schmitt_en No No No OUTPUT
mio_attr_o[31].od_en No No No OUTPUT
mio_attr_o[31].slew_rate[1:0] No No No OUTPUT
mio_attr_o[31].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[31].drive_strength[3:1] No No No OUTPUT
mio_attr_o[32].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[32].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[32].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[32].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[32].keep_en No No No OUTPUT
mio_attr_o[32].schmitt_en No No No OUTPUT
mio_attr_o[32].od_en No No No OUTPUT
mio_attr_o[32].slew_rate[1:0] No No No OUTPUT
mio_attr_o[32].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[32].drive_strength[3:1] No No No OUTPUT
mio_attr_o[33].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[33].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[33].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[33].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[33].keep_en No No No OUTPUT
mio_attr_o[33].schmitt_en No No No OUTPUT
mio_attr_o[33].od_en No No No OUTPUT
mio_attr_o[33].slew_rate[1:0] No No No OUTPUT
mio_attr_o[33].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[33].drive_strength[3:1] No No No OUTPUT
mio_attr_o[34].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[34].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[34].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[34].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[34].keep_en No No No OUTPUT
mio_attr_o[34].schmitt_en No No No OUTPUT
mio_attr_o[34].od_en No No No OUTPUT
mio_attr_o[34].slew_rate[1:0] No No No OUTPUT
mio_attr_o[34].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[34].drive_strength[3:1] No No No OUTPUT
mio_attr_o[35].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[35].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[35].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[35].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[35].keep_en No No No OUTPUT
mio_attr_o[35].schmitt_en No No No OUTPUT
mio_attr_o[35].od_en No No No OUTPUT
mio_attr_o[35].slew_rate[1:0] No No No OUTPUT
mio_attr_o[35].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[35].drive_strength[3:1] No No No OUTPUT
mio_attr_o[36].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[36].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[36].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[36].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[36].keep_en No No No OUTPUT
mio_attr_o[36].schmitt_en No No No OUTPUT
mio_attr_o[36].od_en No No No OUTPUT
mio_attr_o[36].slew_rate[1:0] No No No OUTPUT
mio_attr_o[36].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[36].drive_strength[3:1] No No No OUTPUT
mio_attr_o[37].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[37].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[37].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[37].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[37].keep_en No No No OUTPUT
mio_attr_o[37].schmitt_en No No No OUTPUT
mio_attr_o[37].od_en No No No OUTPUT
mio_attr_o[37].slew_rate[1:0] No No No OUTPUT
mio_attr_o[37].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[37].drive_strength[3:1] No No No OUTPUT
mio_attr_o[38].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[38].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[38].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[38].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[38].keep_en No No No OUTPUT
mio_attr_o[38].schmitt_en No No No OUTPUT
mio_attr_o[38].od_en No No No OUTPUT
mio_attr_o[38].slew_rate[1:0] No No No OUTPUT
mio_attr_o[38].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[38].drive_strength[3:1] No No No OUTPUT
mio_attr_o[39].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[39].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[39].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[39].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[39].keep_en No No No OUTPUT
mio_attr_o[39].schmitt_en No No No OUTPUT
mio_attr_o[39].od_en No No No OUTPUT
mio_attr_o[39].slew_rate[1:0] No No No OUTPUT
mio_attr_o[39].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[39].drive_strength[3:1] No No No OUTPUT
mio_attr_o[40].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[40].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[40].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[40].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[40].keep_en No No No OUTPUT
mio_attr_o[40].schmitt_en No No No OUTPUT
mio_attr_o[40].od_en No No No OUTPUT
mio_attr_o[40].slew_rate[1:0] No No No OUTPUT
mio_attr_o[40].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[40].drive_strength[3:1] No No No OUTPUT
mio_attr_o[41].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[41].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[41].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[41].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[41].keep_en No No No OUTPUT
mio_attr_o[41].schmitt_en No No No OUTPUT
mio_attr_o[41].od_en No No No OUTPUT
mio_attr_o[41].slew_rate[1:0] No No No OUTPUT
mio_attr_o[41].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[41].drive_strength[3:1] No No No OUTPUT
mio_attr_o[42].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[42].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[42].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[42].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[42].keep_en No No No OUTPUT
mio_attr_o[42].schmitt_en No No No OUTPUT
mio_attr_o[42].od_en No No No OUTPUT
mio_attr_o[42].slew_rate[1:0] No No No OUTPUT
mio_attr_o[42].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[42].drive_strength[3:1] No No No OUTPUT
mio_attr_o[43].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[43].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[43].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[43].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[43].keep_en No No No OUTPUT
mio_attr_o[43].schmitt_en No No No OUTPUT
mio_attr_o[43].od_en No No No OUTPUT
mio_attr_o[43].slew_rate[1:0] No No No OUTPUT
mio_attr_o[43].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[43].drive_strength[3:1] No No No OUTPUT
mio_attr_o[44].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[44].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[44].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[44].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[44].keep_en No No No OUTPUT
mio_attr_o[44].schmitt_en No No No OUTPUT
mio_attr_o[44].od_en No No No OUTPUT
mio_attr_o[44].slew_rate[1:0] No No No OUTPUT
mio_attr_o[44].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[44].drive_strength[3:1] No No No OUTPUT
mio_attr_o[45].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[45].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[45].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[45].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[45].keep_en No No No OUTPUT
mio_attr_o[45].schmitt_en No No No OUTPUT
mio_attr_o[45].od_en No No No OUTPUT
mio_attr_o[45].slew_rate[1:0] No No No OUTPUT
mio_attr_o[45].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[45].drive_strength[3:1] No No No OUTPUT
mio_attr_o[46].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[46].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[46].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[46].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[46].keep_en No No No OUTPUT
mio_attr_o[46].schmitt_en No No No OUTPUT
mio_attr_o[46].od_en No No No OUTPUT
mio_attr_o[46].slew_rate[1:0] No No No OUTPUT
mio_attr_o[46].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
mio_attr_o[46].drive_strength[3:1] No No No OUTPUT
mio_out_o[46:0] Yes Yes T12,T14,T23 Yes T12,T14,T23 OUTPUT
mio_oe_o[46:0] Yes Yes T12,T24,T25 Yes T12,T14,T23 OUTPUT
mio_in_i[46:0] Yes Yes T12,T13,T14 Yes T12,T13,T14 INPUT
dio_attr_o[0].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[0].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[0].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[0].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[0].keep_en No No No OUTPUT
dio_attr_o[0].schmitt_en No No No OUTPUT
dio_attr_o[0].od_en No No No OUTPUT
dio_attr_o[0].slew_rate[1:0] No No No OUTPUT
dio_attr_o[0].drive_strength[0] Yes Yes *T2,*T3,*T29 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].drive_strength[3:1] No No No OUTPUT
dio_attr_o[1].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[1].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[1].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[1].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[1].keep_en No No No OUTPUT
dio_attr_o[1].schmitt_en No No No OUTPUT
dio_attr_o[1].od_en No No No OUTPUT
dio_attr_o[1].slew_rate[1:0] No No No OUTPUT
dio_attr_o[1].drive_strength[0] Yes Yes *T2,*T3,*T29 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].drive_strength[3:1] No No No OUTPUT
dio_attr_o[2].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[2].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[2].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
dio_attr_o[2].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
dio_attr_o[2].keep_en No No No OUTPUT
dio_attr_o[2].schmitt_en No No No OUTPUT
dio_attr_o[2].od_en No No No OUTPUT
dio_attr_o[2].slew_rate[1:0] No No No OUTPUT
dio_attr_o[2].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[2].drive_strength[3:1] No No No OUTPUT
dio_attr_o[3].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[3].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[3].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
dio_attr_o[3].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
dio_attr_o[3].keep_en No No No OUTPUT
dio_attr_o[3].schmitt_en No No No OUTPUT
dio_attr_o[3].od_en No No No OUTPUT
dio_attr_o[3].slew_rate[1:0] No No No OUTPUT
dio_attr_o[3].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[3].drive_strength[3:1] No No No OUTPUT
dio_attr_o[4].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[4].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[4].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
dio_attr_o[4].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
dio_attr_o[4].keep_en No No No OUTPUT
dio_attr_o[4].schmitt_en No No No OUTPUT
dio_attr_o[4].od_en No No No OUTPUT
dio_attr_o[4].slew_rate[1:0] No No No OUTPUT
dio_attr_o[4].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[4].drive_strength[3:1] No No No OUTPUT
dio_attr_o[5].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[5].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[5].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
dio_attr_o[5].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T9 OUTPUT
dio_attr_o[5].keep_en No No No OUTPUT
dio_attr_o[5].schmitt_en No No No OUTPUT
dio_attr_o[5].od_en No No No OUTPUT
dio_attr_o[5].slew_rate[1:0] No No No OUTPUT
dio_attr_o[5].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[5].drive_strength[3:1] No No No OUTPUT
dio_attr_o[6].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[6].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[6].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[6].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[6].keep_en No No No OUTPUT
dio_attr_o[6].schmitt_en No No No OUTPUT
dio_attr_o[6].od_en No No No OUTPUT
dio_attr_o[6].slew_rate[1:0] No No No OUTPUT
dio_attr_o[6].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[6].drive_strength[3:1] No No No OUTPUT
dio_attr_o[7].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[7].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[7].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[7].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[7].keep_en No No No OUTPUT
dio_attr_o[7].schmitt_en No No No OUTPUT
dio_attr_o[7].od_en No No No OUTPUT
dio_attr_o[7].slew_rate[1:0] No No No OUTPUT
dio_attr_o[7].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[7].drive_strength[3:1] No No No OUTPUT
dio_attr_o[8].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[8].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[8].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[8].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[8].keep_en No No No OUTPUT
dio_attr_o[8].schmitt_en No No No OUTPUT
dio_attr_o[8].od_en No No No OUTPUT
dio_attr_o[8].slew_rate[1:0] No No No OUTPUT
dio_attr_o[8].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[8].drive_strength[3:1] No No No OUTPUT
dio_attr_o[9].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[9].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[9].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[9].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[9].keep_en No No No OUTPUT
dio_attr_o[9].schmitt_en No No No OUTPUT
dio_attr_o[9].od_en No No No OUTPUT
dio_attr_o[9].slew_rate[1:0] No No No OUTPUT
dio_attr_o[9].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[9].drive_strength[3:1] No No No OUTPUT
dio_attr_o[10].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[10].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[10].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[10].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[10].keep_en No No No OUTPUT
dio_attr_o[10].schmitt_en No No No OUTPUT
dio_attr_o[10].od_en No No No OUTPUT
dio_attr_o[10].slew_rate[1:0] No No No OUTPUT
dio_attr_o[10].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[10].drive_strength[3:1] No No No OUTPUT
dio_attr_o[11].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[11].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[11].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[11].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[11].keep_en No No No OUTPUT
dio_attr_o[11].schmitt_en No No No OUTPUT
dio_attr_o[11].od_en No No No OUTPUT
dio_attr_o[11].slew_rate[1:0] No No No OUTPUT
dio_attr_o[11].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[11].drive_strength[3:1] No No No OUTPUT
dio_attr_o[12].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[12].virt_od_en No No No OUTPUT
dio_attr_o[12].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[12].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[12].keep_en No No No OUTPUT
dio_attr_o[12].schmitt_en No No No OUTPUT
dio_attr_o[12].od_en No No No OUTPUT
dio_attr_o[12].slew_rate[1:0] No No No OUTPUT
dio_attr_o[12].drive_strength[3:0] No No No OUTPUT
dio_attr_o[13].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[13].virt_od_en No No No OUTPUT
dio_attr_o[13].pull_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[13].pull_select Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[13].keep_en No No No OUTPUT
dio_attr_o[13].schmitt_en No No No OUTPUT
dio_attr_o[13].od_en No No No OUTPUT
dio_attr_o[13].slew_rate[1:0] No No No OUTPUT
dio_attr_o[13].drive_strength[3:0] No No No OUTPUT
dio_attr_o[14].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[14].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[14].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
dio_attr_o[14].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
dio_attr_o[14].keep_en No No No OUTPUT
dio_attr_o[14].schmitt_en No No No OUTPUT
dio_attr_o[14].od_en No No No OUTPUT
dio_attr_o[14].slew_rate[1:0] No No No OUTPUT
dio_attr_o[14].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[14].drive_strength[3:1] No No No OUTPUT
dio_attr_o[15].invert Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[15].virt_od_en Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[15].pull_en Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
dio_attr_o[15].pull_select Yes Yes T26,T27,T28 Yes T30,T31,T32 OUTPUT
dio_attr_o[15].keep_en No No No OUTPUT
dio_attr_o[15].schmitt_en No No No OUTPUT
dio_attr_o[15].od_en No No No OUTPUT
dio_attr_o[15].slew_rate[1:0] No No No OUTPUT
dio_attr_o[15].drive_strength[0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
dio_attr_o[15].drive_strength[3:1] No No No OUTPUT
dio_out_o[11:0] Yes Yes *T15,*T16,*T17 Yes T16,T17,T18 OUTPUT
dio_out_o[13:12] No No No OUTPUT
dio_out_o[15:14] Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT
dio_oe_o[15:0] Yes Yes T16,T17,T22 Yes T16,T17,T22 OUTPUT
dio_in_i[15:0] Yes Yes T15,T16,T17 Yes T16,T17,T18 INPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : pinmux
Line No.TotalCoveredPercent
Branches 776 665 85.70
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 2 50.00
TERNARY 486 4 2 50.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 2 50.00
TERNARY 486 4 2 50.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 2 50.00
TERNARY 486 4 2 50.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 2 50.00
TERNARY 486 4 2 50.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 2 50.00
TERNARY 486 4 2 50.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 2 50.00
TERNARY 486 4 2 50.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 3 75.00
TERNARY 486 4 3 75.00
TERNARY 469 2 2 100.00
TERNARY 473 2 2 100.00
TERNARY 482 4 4 100.00
TERNARY 486 4 4 100.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 4 100.00
TERNARY 522 4 4 100.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 4 100.00
TERNARY 522 4 4 100.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 3 75.00
TERNARY 522 4 3 75.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 3 75.00
TERNARY 522 4 3 75.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 3 75.00
TERNARY 522 4 3 75.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 3 75.00
TERNARY 522 4 3 75.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 3 75.00
TERNARY 522 4 3 75.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 2 50.00
TERNARY 522 4 2 50.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 3 75.00
TERNARY 522 4 3 75.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 4 100.00
TERNARY 522 4 4 100.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 4 100.00
TERNARY 522 4 4 100.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 3 75.00
TERNARY 522 4 3 75.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 2 50.00
TERNARY 522 4 2 50.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 2 50.00
TERNARY 522 4 2 50.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 2 50.00
TERNARY 522 4 2 50.00
TERNARY 505 2 2 100.00
TERNARY 509 2 2 100.00
TERNARY 518 4 2 50.00
TERNARY 522 4 2 50.00
TERNARY 551 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 551 2 1 50.00
TERNARY 551 2 2 100.00
IF 161 2 2 100.00
IF 413 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[0].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[0].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T50
0 1 - Covered T14,T44,T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T50
0 1 - Covered T14,T44,T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[1].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[1].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T50
0 1 - Covered T14,T44,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T50
0 1 - Covered T14,T44,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[2].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[2].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T45
0 1 - Covered T14,T44,T6
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T45
0 1 - Covered T14,T44,T6
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[3].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[3].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T45
0 1 - Covered T14,T44,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T45
0 1 - Covered T14,T44,T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[4].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[4].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T50
0 1 - Covered T14,T44,T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T50
0 1 - Covered T14,T44,T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[5].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[5].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T50
0 1 - Covered T14,T44,T50
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45,T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T50
0 1 - Covered T14,T44,T50
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45,T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[6].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[6].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T50
0 1 - Covered T14,T44,T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T50
0 1 - Covered T14,T44,T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[7].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[7].q) ?

Branches:
-1-StatusTests
1 Covered T14,T44,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T50
0 1 - Covered T14,T44,T6
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T14,T44,T50
0 1 - Covered T14,T44,T6
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[8].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[8].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T48
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T48
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[9].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[9].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T45
0 1 - Covered T48,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T45
0 1 - Covered T48,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[10].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[10].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45,T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45,T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[11].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[11].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T48,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T48,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[12].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[12].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T6,T48
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T6,T48
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[13].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[13].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T48,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T48,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[14].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[14].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T45,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T45,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[15].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[15].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[16].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[16].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[17].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[17].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T8
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T8
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[18].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[18].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T45
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T45
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[19].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[19].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T48
0 1 - Covered T7,T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T48
0 1 - Covered T7,T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[20].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[20].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[21].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[21].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T48
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T48
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[22].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[22].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T48
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T48
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[23].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[23].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T48
0 1 - Covered T6,T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T48
0 1 - Covered T6,T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[24].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[24].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[25].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[25].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T48
0 1 - Covered T6,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T48
0 1 - Covered T6,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[26].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[26].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45,T8
0 1 - Covered T6,T48
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45,T8
0 1 - Covered T6,T48
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[27].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[27].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45
0 1 - Covered T6,T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45
0 1 - Covered T6,T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[28].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[28].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T48,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T48,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[29].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[29].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T6,T48
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T6,T48
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[30].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[30].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45,T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45,T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[31].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[31].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[32].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[32].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T48,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T48,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[33].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[33].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T48
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T48
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[34].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[34].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T48
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T48
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[35].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[35].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T48
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T48
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[36].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[36].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45
0 1 - Covered T6,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45
0 1 - Covered T6,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[37].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[37].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T48
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T48
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[38].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[38].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T45,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T7,T45,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[39].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[39].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[40].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[40].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[41].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[41].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45
0 1 - Covered T6,T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45
0 1 - Covered T6,T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[42].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[42].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[43].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[43].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T8
0 1 - Covered T7,T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T8
0 1 - Covered T7,T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[44].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[44].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T8
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T8
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[45].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[45].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T6,T45,T48
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T6,T45,T48
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 469 (reg2hw.mio_pad_sleep_status[46].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 473 (reg2hw.mio_pad_sleep_status[46].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 482 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? -2-: 482 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? -3-: 482 ((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T6,T45
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 486 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? -2-: 486 ((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? -3-: 486 ((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T6,T45
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[0].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[0].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[1].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[1].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7,T48
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7,T48
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[2].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[2].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T48
0 1 - Covered T7,T45,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T48
0 1 - Covered T7,T45,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[3].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[3].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T48
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T48
0 1 - Covered T7,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[4].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[4].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[5].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[5].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T45,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7
0 1 - Covered T45,T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[6].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[6].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T48
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T48
0 1 - Covered T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[7].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[7].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T8
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[8].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[8].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[9].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[9].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T8
0 1 - Covered T7
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[10].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[10].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T48
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T48
0 1 - Covered T6
0 0 1 Covered T1,T2,T3
0 0 0 Covered T45


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[11].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[11].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T48


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[12].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[12].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T48
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T48
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[13].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[13].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[14].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[14].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T7,T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Covered T6,T7,T45
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 505 (reg2hw.dio_pad_sleep_status[15].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 509 (reg2hw.dio_pad_sleep_status[15].q) ?

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 518 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? -2-: 518 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? -3-: 518 ((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 522 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? -2-: 522 ((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? -3-: 522 ((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T45,T8
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 551 (reg2hw.wkup_detector[0].miodio.q) ?

Branches:
-1-StatusTests
1 Covered T48
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (reg2hw.wkup_detector[1].miodio.q) ?

Branches:
-1-StatusTests
1 Covered T45
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (reg2hw.wkup_detector[2].miodio.q) ?

Branches:
-1-StatusTests
1 Covered T45
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (reg2hw.wkup_detector[3].miodio.q) ?

Branches:
-1-StatusTests
1 Covered T45
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (reg2hw.wkup_detector[4].miodio.q) ?

Branches:
-1-StatusTests
1 Covered T43,T48
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (reg2hw.wkup_detector[5].miodio.q) ?

Branches:
-1-StatusTests
1 Covered T42,T49
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (reg2hw.wkup_detector[6].miodio.q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (reg2hw.wkup_detector[7].miodio.q) ?

Branches:
-1-StatusTests
1 Covered T45
0 Covered T1,T2,T3


LineNo. Expression -1-: 161 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 413 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : pinmux
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 25 25 100.00 23 92.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 25 25 100.00 23 92.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 100897745 100261660 0 0
AonWkupReqKnownO_A 1329713 1154772 0 0
DftJtagTckKnown_A 100897745 100261660 0 0
DftJtagTmsKnown_A 100897745 100261660 0 0
DftJtagTrstKnown_A 100897745 100261660 0 0
DftStrapsKnown_A 100897745 100261660 0 0
DioKnownO_A 100897745 100261660 0 0
DioOeKnownO_A 100897745 100261660 0 0
FpvSecCmBusIntegrity_A 100897745 0 0 0
FpvSecCmRegWeOnehotCheck_A 100897745 4 0 0
LcJtagTckKnown_A 100897745 100261660 0 0
LcJtagTmsKnown_A 100897745 100261660 0 0
LcJtagTrstKnown_A 100897745 100261660 0 0
MioKnownO_A 100897745 100261660 0 0
MioOeKnownO_A 100897745 100261660 0 0
PinmuxWkupStable_A 1329713 1157 0 0
PwrMgrStrapSampleOnce0_A 100897745 1626 0 0
PwrMgrStrapSampleOnce1_A 100897745 0 0 907
RvJtagTckKnown_A 100897745 100261660 0 0
RvJtagTmsKnown_A 100897745 100261660 0 0
RvJtagTrstKnown_A 100897745 100261660 0 0
TlAReadyKnownO_A 100897745 100261660 0 0
TlDValidKnownO_A 100897745 100261660 0 0
UsbWakeDetectActiveKnownO_A 1329713 1154772 0 0
UsbWkupReqKnownO_A 1329713 1154772 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

AonWkupReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1329713 1154772 0 0
T1 509 347 0 0
T2 4112 3332 0 0
T3 857 692 0 0
T4 2749 2467 0 0
T39 1662 1500 0 0
T40 1618 1454 0 0
T51 495 331 0 0
T52 664 500 0 0
T85 431 269 0 0
T86 457 295 0 0

DftJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

DftJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

DftJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

DftStrapsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

DioKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

DioOeKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

FpvSecCmBusIntegrity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 4 0 0
T81 36492 1 0 0
T87 0 1 0 0
T88 0 1 0 0
T89 0 1 0 0
T90 116817 0 0 0
T91 60283 0 0 0
T92 42590 0 0 0
T93 52330 0 0 0
T94 100362 0 0 0
T95 48002 0 0 0
T96 18376 0 0 0
T97 37247 0 0 0
T98 43915 0 0 0

LcJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

LcJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

LcJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

MioKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

MioOeKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

PinmuxWkupStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1329713 1157 0 0
T13 715 0 0 0
T14 0 89 0 0
T31 398 0 0 0
T37 2210 0 0 0
T42 919 427 0 0
T43 0 22 0 0
T44 0 110 0 0
T49 0 349 0 0
T50 0 160 0 0
T62 6473 0 0 0
T99 785 0 0 0
T100 457 0 0 0
T101 705 0 0 0
T102 636 0 0 0
T103 771 0 0 0

PwrMgrStrapSampleOnce0_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 1626 0 0
T1 21360 1 0 0
T2 245055 11 0 0
T3 55050 2 0 0
T4 284960 3 0 0
T39 168906 1 0 0
T40 170314 1 0 0
T51 35409 1 0 0
T52 39143 1 0 0
T85 22281 1 0 0
T86 29931 1 0 0

PwrMgrStrapSampleOnce1_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 0 0 907

RvJtagTckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

RvJtagTmsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

RvJtagTrstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 100897745 100261660 0 0
T1 21360 21075 0 0
T2 245055 240685 0 0
T3 55050 54585 0 0
T4 284960 283514 0 0
T39 168906 168506 0 0
T40 170314 169707 0 0
T51 35409 34658 0 0
T52 39143 38829 0 0
T85 22281 21852 0 0
T86 29931 29371 0 0

UsbWakeDetectActiveKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1329713 1154772 0 0
T1 509 347 0 0
T2 4112 3332 0 0
T3 857 692 0 0
T4 2749 2467 0 0
T39 1662 1500 0 0
T40 1618 1454 0 0
T51 495 331 0 0
T52 664 500 0 0
T85 431 269 0 0
T86 457 295 0 0

UsbWkupReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1329713 1154772 0 0
T1 509 347 0 0
T2 4112 3332 0 0
T3 857 692 0 0
T4 2749 2467 0 0
T39 1662 1500 0 0
T40 1618 1454 0 0
T51 495 331 0 0
T52 664 500 0 0
T85 431 269 0 0
T86 457 295 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%