Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400542454	44416209	0	0
DepthKnown_A	400542454	400442675	0	0
RvalidKnown_A	400542454	400442675	0	0
WreadyKnown_A	400542454	400442675	0	0
gen_passthru_fifo.paramCheckPass	953	953	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	44416209	0	0
T1	86272	9054	0	0
T2	815654	380243	0	0
T3	224354	22065	0	0
T4	605918	424156	0	0
T39	700521	85738	0	0
T40	705530	86898	0	0
T51	127175	17590	0	0
T52	144050	20142	0	0
T85	89510	10390	0	0
T86	111675	12782	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	953	953	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400542454	33741751	0	0
DepthKnown_A	400542454	400442675	0	0
RvalidKnown_A	400542454	400442675	0	0
WreadyKnown_A	400542454	400442675	0	0
gen_passthru_fifo.paramCheckPass	953	953	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	33741751	0	0
T1	86272	7373	0	0
T2	815654	195034	0	0
T3	224354	15111	0	0
T4	605918	214575	0	0
T39	700521	68121	0	0
T40	705530	69155	0	0
T51	127175	12147	0	0
T52	144050	14698	0	0
T85	89510	8007	0	0
T86	111675	10512	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	953	953	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400542454	30286588	0	0
DepthKnown_A	400542454	400442675	0	0
RvalidKnown_A	400542454	400442675	0	0
WreadyKnown_A	400542454	400442675	0	0
gen_passthru_fifo.paramCheckPass	953	953	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	30286588	0	0
T1	86272	5777	0	0
T2	815654	36349	0	0
T3	224354	10270	0	0
T4	605918	94343	0	0
T39	700521	145833	0	0
T40	705530	135639	0	0
T51	127175	6511	0	0
T52	144050	8361	0	0
T85	89510	5598	0	0
T86	111675	10483	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	953	953	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400542454	24929265	0	0
DepthKnown_A	400542454	400442675	0	0
RvalidKnown_A	400542454	400442675	0	0
WreadyKnown_A	400542454	400442675	0	0
gen_passthru_fifo.paramCheckPass	953	953	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	24929265	0	0
T1	86272	5664	0	0
T2	815654	33475	0	0
T3	224354	9928	0	0
T4	605918	35884	0	0
T39	700521	59965	0	0
T40	705530	61340	0	0
T51	127175	6232	0	0
T52	144050	8082	0	0
T85	89510	5470	0	0
T86	111675	10128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	400442675	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	953	953	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476455720	85582	0	0
DepthKnown_A	476455720	476344384	0	0
RvalidKnown_A	476455720	476344384	0	0
WreadyKnown_A	476455720	476344384	0	0
gen_passthru_fifo.paramCheckPass	2844	2844	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	85582	0	0
T1	86272	13	0	0
T2	815654	98	0	0
T3	224354	102	0	0
T4	605918	16	0	0
T39	700521	26	0	0
T40	705530	26	0	0
T51	127175	26	0	0
T52	144050	26	0	0
T85	89510	13	0	0
T86	111675	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2844	2844	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476455720	88175	0	0
DepthKnown_A	476455720	476344384	0	0
RvalidKnown_A	476455720	476344384	0	0
WreadyKnown_A	476455720	476344384	0	0
gen_passthru_fifo.paramCheckPass	2844	2844	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	88175	0	0
T1	86272	13	0	0
T2	815654	98	0	0
T3	224354	102	0	0
T4	605918	16	0	0
T39	700521	26	0	0
T40	705530	26	0	0
T51	127175	26	0	0
T52	144050	26	0	0
T85	89510	13	0	0
T86	111675	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2844	2844	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476455720	48761	0	0
DepthKnown_A	476455720	476344384	0	0
RvalidKnown_A	476455720	476344384	0	0
WreadyKnown_A	476455720	476344384	0	0
gen_passthru_fifo.paramCheckPass	2844	2844	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	48761	0	0
T1	86272	12	0	0
T2	815654	98	0	0
T3	224354	94	0	0
T4	605918	5	0	0
T39	700521	5	0	0
T40	705530	5	0	0
T51	127175	23	0	0
T52	144050	23	0	0
T85	89510	12	0	0
T86	111675	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2844	2844	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476455720	48761	0	0
DepthKnown_A	476455720	476344384	0	0
RvalidKnown_A	476455720	476344384	0	0
WreadyKnown_A	476455720	476344384	0	0
gen_passthru_fifo.paramCheckPass	2844	2844	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	48761	0	0
T1	86272	12	0	0
T2	815654	98	0	0
T3	224354	94	0	0
T4	605918	5	0	0
T39	700521	5	0	0
T40	705530	5	0	0
T51	127175	23	0	0
T52	144050	23	0	0
T85	89510	12	0	0
T86	111675	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2844	2844	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476455720	36821	0	0
DepthKnown_A	476455720	476344384	0	0
RvalidKnown_A	476455720	476344384	0	0
WreadyKnown_A	476455720	476344384	0	0
gen_passthru_fifo.paramCheckPass	2844	2844	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	36821	0	0
T1	86272	1	0	0
T2	815654	0	0	0
T3	224354	8	0	0
T4	605918	11	0	0
T39	700521	21	0	0
T40	705530	21	0	0
T41	0	21	0	0
T51	127175	3	0	0
T52	144050	3	0	0
T85	89510	1	0	0
T86	111675	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2844	2844	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476455720	39414	0	0
DepthKnown_A	476455720	476344384	0	0
RvalidKnown_A	476455720	476344384	0	0
WreadyKnown_A	476455720	476344384	0	0
gen_passthru_fifo.paramCheckPass	2844	2844	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	39414	0	0
T1	86272	1	0	0
T2	815654	0	0	0
T3	224354	8	0	0
T4	605918	11	0	0
T39	700521	21	0	0
T40	705530	21	0	0
T41	0	21	0	0
T51	127175	3	0	0
T52	144050	3	0	0
T85	89510	1	0	0
T86	111675	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476455720	476344384	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2844	2844	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0