Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.27 98.27

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 100.00 100.00
tb.dut.top_earlgrey.u_sram_ctrl_main 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.73 90.65 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.73 90.65 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 64 60 93.75
Total Bits 1158 1138 98.27
Total Bits 0->1 579 569 98.27
Total Bits 1->0 579 569 98.27

Ports 64 60 93.75
Port Bits 1158 1138 98.27
Port Bits 0->1 579 569 98.27
Port Bits 1->0 579 569 98.27

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[16:0] Yes Yes *T75,*T57,*T76 Yes T75,T57,T76 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T75,T57,T76 Yes T75,T57,T76 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T4 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_sink Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[4:0] Yes Yes *T75,*T57,*T76 Yes T75,T57,T76 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T39,*T4,*T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T4,*T71,*T77 Yes T4,T71,T77 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T75,T57,T76 Yes T75,T57,T76 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T71,T78,T45 Yes T71,T78,T45 INPUT
regs_tl_i.a_valid Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_o.a_ready Yes Yes T39,T4,T40 Yes T39,T4,T40 OUTPUT
regs_tl_o.d_error Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T131,T139,T140 Yes T131,T139,T140 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T131,T36,T139 Yes T39,T4,T40 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T131,T36,T139 Yes T39,T4,T40 OUTPUT
regs_tl_o.d_sink Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes T75,*T76,*T79 Yes T75,T76,T79 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T75,T57,T76 Yes T75,T57,T76 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T131,*T139,*T140 Yes T131,T411,T139 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T39,T4,T40 Yes T39,T4,T40 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T82,T251,T83 Yes T82,T251,T83 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T82,T251,T83 Yes T82,T251,T83 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T3,T65,T66 Yes T3,T65,T66 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T3,T4,T29 Yes T1,T3,T51 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
sram_otp_key_o.req Yes Yes T39,T4,T40 Yes T39,T4,T40 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T2,T3,T29 Yes T1,T2,T3 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T2,T3,T39 Yes T1,T2,T3 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T3 Yes T2,T3,T39 INPUT
sram_otp_key_i.ack Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 58 58 100.00
Total Bits 1096 1096 100.00
Total Bits 0->1 548 548 100.00
Total Bits 1->0 548 548 100.00

Ports 58 58 100.00
Port Bits 1096 1096 100.00
Port Bits 0->1 548 548 100.00
Port Bits 1->0 548 548 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T2,T3,T39 Yes T2,T3,T39 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[11:0] Yes Yes *T75,*T57,*T76 Yes T75,T57,T76 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T4,*T71,*T77 Yes T4,T71,T77 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T75,T57,T76 Yes T75,T57,T76 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T71,T78,T45 Yes T71,T78,T45 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T4 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T39 Yes T2,T3,T39 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T2,T3,T39 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T2,T3,T39 Yes T2,T3,T39 OUTPUT
ram_tl_o.d_sink Yes Yes T75,T107,T80 Yes T75,T107,T80 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T71,*T78,*T412 Yes T71,T78,T412 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T75,T107,T80 Yes T75,T107,T80 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T3,*T39 Yes T1,T3,T39 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[4:0] Yes Yes *T75,*T57,*T76 Yes T75,T57,T76 INPUT
regs_tl_i.a_address[19:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T4,*T71,*T77 Yes T4,T71,T77 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T75,T57,T76 Yes T75,T57,T76 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T71,T78,T45 Yes T71,T78,T45 INPUT
regs_tl_i.a_valid Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_o.a_ready Yes Yes T39,T4,T40 Yes T39,T4,T40 OUTPUT
regs_tl_o.d_error Yes Yes T75,T80,T241 Yes T75,T80,T241 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T131,T139,T140 Yes T131,T139,T140 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T131,T36,T139 Yes T39,T4,T40 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T131,T36,T139 Yes T39,T4,T40 OUTPUT
regs_tl_o.d_sink Yes Yes T75,T107,T80 Yes T75,T107,T80 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T75,*T80,*T157 Yes T75,T107,T80 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T75,T57,T107 Yes T75,T57,T107 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T131,*T139,*T140 Yes T131,T411,T139 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T39,T4,T40 Yes T39,T4,T40 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T82,T83,T53 Yes T82,T83,T53 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T83,T84 Yes T82,T84,T413 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T84,T413 Yes T82,T83,T84 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T82,T83,T53 Yes T82,T83,T53 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T3,T65,T66 Yes T3,T65,T66 INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req Yes Yes T131,T139,T140 Yes T131,T139,T140 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T2,T3,T29 Yes T1,T2,T3 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T2,T3,T39 Yes T1,T2,T3 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T3 Yes T2,T3,T39 INPUT
sram_otp_key_i.ack Yes Yes T131,T139,T140 Yes T131,T139,T140 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 60 60 100.00
Total Bits 1130 1130 100.00
Total Bits 0->1 565 565 100.00
Total Bits 1->0 565 565 100.00

Ports 60 60 100.00
Port Bits 1130 1130 100.00
Port Bits 0->1 565 565 100.00
Port Bits 1->0 565 565 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[16:0] Yes Yes *T75,*T76,*T79 Yes T75,T76,T79 INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T75,T76,T79 Yes T75,T76,T79 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T2,T3,T4 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_sink Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T2,T3,T39 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_address[4:0] Yes Yes *T75,*T76,*T80 Yes T75,T76,T80 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T39,*T4,*T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T39,*T4,*T40 Yes T39,T4,T40 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T75,*T76,*T79 Yes T75,T76,T79 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T75,T57,T76 Yes T75,T57,T76 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T75,T57,T76 Yes T75,T57,T76 INPUT
regs_tl_i.a_valid Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
regs_tl_o.a_ready Yes Yes T39,T4,T40 Yes T39,T4,T40 OUTPUT
regs_tl_o.d_error Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T75,T57,T76 Yes T75,T57,T76 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T131,T36,T139 Yes T39,T4,T40 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T131,T36,T139 Yes T39,T4,T40 OUTPUT
regs_tl_o.d_sink Yes Yes T75,T76,T79 Yes T75,T76,T79 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes T75,*T76,*T79 Yes T75,T76,T79 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T75,T57,T76 Yes T75,T57,T76 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T131,*T139,*T140 Yes T131,T411,T139 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T39,T4,T40 Yes T39,T4,T40 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T82,T251,T83 Yes T82,T251,T83 INPUT
alert_rx_i[0].ping_n Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT
alert_rx_i[0].ping_p Yes Yes T82,T83,T84 Yes T82,T83,T84 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T82,T251,T83 Yes T82,T251,T83 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T3,T65,T66 Yes T3,T65,T66 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T3,T4,T29 Yes T1,T3,T51 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
sram_otp_key_o.req Yes Yes T39,T4,T40 Yes T39,T4,T40 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T2,T3,T29 Yes T1,T2,T3 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T2,T3,T39 Yes T1,T2,T3 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T3 Yes T2,T3,T39 INPUT
sram_otp_key_i.ack Yes Yes T39,T4,T40 Yes T39,T4,T40 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%