Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.97 100.00 99.90 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.97 100.00 99.90 100.00 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15281528100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
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CONT_ASSIGN11911100.00
CONT_ASSIGN1622711100.00
CONT_ASSIGN1624111100.00
CONT_ASSIGN1627511100.00
CONT_ASSIGN1628911100.00
ALWAYS16295199199100.00
CONT_ASSIGN1649611100.00
ALWAYS1650011100.00
CONT_ASSIGN1670211100.00
CONT_ASSIGN1670411100.00
CONT_ASSIGN1670511100.00
CONT_ASSIGN1670711100.00
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CONT_ASSIGN1674011100.00
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CONT_ASSIGN1675011100.00
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CONT_ASSIGN1703411100.00
CONT_ASSIGN1703511100.00
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CONT_ASSIGN1721811100.00
CONT_ASSIGN1722011100.00
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CONT_ASSIGN1723811100.00
CONT_ASSIGN1723911100.00
CONT_ASSIGN1724111100.00
CONT_ASSIGN1724211100.00
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CONT_ASSIGN1731011100.00
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CONT_ASSIGN1731311100.00
CONT_ASSIGN1731511100.00
CONT_ASSIGN1731711100.00
CONT_ASSIGN1731911100.00
CONT_ASSIGN1732111100.00
CONT_ASSIGN1732311100.00
CONT_ASSIGN1732511100.00
CONT_ASSIGN1732711100.00
CONT_ASSIGN1732911100.00
CONT_ASSIGN1733111100.00
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CONT_ASSIGN1759111100.00
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CONT_ASSIGN1760111100.00
CONT_ASSIGN1760311100.00
CONT_ASSIGN1760511100.00
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CONT_ASSIGN1762711100.00
CONT_ASSIGN1762811100.00
CONT_ASSIGN1763011100.00
ALWAYS17634199199100.00
ALWAYS17837552552100.00
CONT_ASSIGN1899400
CONT_ASSIGN1900211100.00
CONT_ASSIGN1900311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16227 1 1
16241 1 1
16275 1 1
16289 1 1
16295 1 1
16296 1 1
16297 1 1
16298 1 1
16299 1 1
16300 1 1
16301 1 1
16302 1 1
16303 1 1
16304 1 1
16305 1 1
16306 1 1
16307 1 1
16308 1 1
16309 1 1
16310 1 1
16311 1 1
16312 1 1
16313 1 1
16314 1 1
16315 1 1
16316 1 1
16317 1 1
16318 1 1
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16320 1 1
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16322 1 1
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16326 1 1
16327 1 1
16328 1 1
16329 1 1
16330 1 1
16331 1 1
16332 1 1
16333 1 1
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16335 1 1
16336 1 1
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18964 1 1
18968 1 1
18972 1 1
18976 1 1
18980 1 1
18994 unreachable
19002 1 1
19003 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions1983198199.90
Logical1983198199.90
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1647699.73
16477-16500100.00
16500100.00
16500-16978100.00
16981-1762899.75

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 204 204 100.00
TERNARY 16496 2 2 100.00
IF 68 3 3 100.00
CASE 17838 199 199 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16496 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T3,T51,T52
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T297,T301,T302
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 17838 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T3,T51,T52
addr_hit[1] Covered T191,T299,T300
addr_hit[2] Covered T191,T299,T300
addr_hit[3] Covered T191,T299,T300
addr_hit[4] Covered T191,T299,T300
addr_hit[5] Covered T191,T299,T300
addr_hit[6] Covered T191,T299,T300
addr_hit[7] Covered T191,T299,T300
addr_hit[8] Covered T191,T299,T300
addr_hit[9] Covered T151,T187,T188
addr_hit[10] Covered T151,T187,T188
addr_hit[11] Covered T151,T187,T188
addr_hit[12] Covered T151,T187,T188
addr_hit[13] Covered T151,T187,T188
addr_hit[14] Covered T151,T187,T188
addr_hit[15] Covered T151,T187,T188
addr_hit[16] Covered T151,T187,T188
addr_hit[17] Covered T178,T299,T300
addr_hit[18] Covered T178,T299,T300
addr_hit[19] Covered T178,T299,T300
addr_hit[20] Covered T178,T299,T300
addr_hit[21] Covered T178,T299,T300
addr_hit[22] Covered T178,T299,T300
addr_hit[23] Covered T178,T299,T300
addr_hit[24] Covered T178,T299,T300
addr_hit[25] Covered T299,T13,T300
addr_hit[26] Covered T299,T13,T300
addr_hit[27] Covered T299,T13,T300
addr_hit[28] Covered T299,T13,T300
addr_hit[29] Covered T299,T13,T300
addr_hit[30] Covered T299,T13,T300
addr_hit[31] Covered T299,T13,T300
addr_hit[32] Covered T299,T13,T300
addr_hit[33] Covered T12,T299,T300
addr_hit[34] Covered T12,T299,T300
addr_hit[35] Covered T12,T299,T300
addr_hit[36] Covered T12,T299,T300
addr_hit[37] Covered T12,T299,T300
addr_hit[38] Covered T12,T299,T300
addr_hit[39] Covered T12,T299,T300
addr_hit[40] Covered T12,T299,T300
addr_hit[41] Covered T12,T299,T300
addr_hit[42] Covered T12,T299,T300
addr_hit[43] Covered T12,T299,T300
addr_hit[44] Covered T12,T299,T300
addr_hit[45] Covered T12,T299,T300
addr_hit[46] Covered T12,T299,T300
addr_hit[47] Covered T12,T299,T300
addr_hit[48] Covered T12,T299,T300
addr_hit[49] Covered T12,T299,T300
addr_hit[50] Covered T12,T299,T300
addr_hit[51] Covered T12,T299,T300
addr_hit[52] Covered T12,T299,T300
addr_hit[53] Covered T12,T299,T300
addr_hit[54] Covered T12,T299,T300
addr_hit[55] Covered T12,T299,T300
addr_hit[56] Covered T12,T299,T300
addr_hit[57] Covered T12,T299,T300
addr_hit[58] Covered T12,T299,T300
addr_hit[59] Covered T12,T299,T300
addr_hit[60] Covered T12,T299,T300
addr_hit[61] Covered T12,T299,T300
addr_hit[62] Covered T12,T299,T300
addr_hit[63] Covered T12,T299,T300
addr_hit[64] Covered T12,T299,T300
addr_hit[65] Covered T12,T299,T300
addr_hit[66] Covered T299,T300,T110
addr_hit[67] Covered T299,T300,T110
addr_hit[68] Covered T299,T300,T110
addr_hit[69] Covered T299,T300,T110
addr_hit[70] Covered T299,T300,T110
addr_hit[71] Covered T299,T300,T110
addr_hit[72] Covered T299,T300,T110
addr_hit[73] Covered T299,T300,T110
addr_hit[74] Covered T299,T300,T110
addr_hit[75] Covered T299,T300,T110
addr_hit[76] Covered T299,T300,T110
addr_hit[77] Covered T299,T300,T110
addr_hit[78] Covered T299,T300,T110
addr_hit[79] Covered T299,T300,T110
addr_hit[80] Covered T299,T300,T110
addr_hit[81] Covered T299,T300,T110
addr_hit[82] Covered T299,T300,T110
addr_hit[83] Covered T299,T300,T110
addr_hit[84] Covered T299,T300,T110
addr_hit[85] Covered T299,T300,T110
addr_hit[86] Covered T299,T300,T110
addr_hit[87] Covered T299,T300,T110
addr_hit[88] Covered T299,T300,T189
addr_hit[89] Covered T299,T300,T189
addr_hit[90] Covered T299,T300,T110
addr_hit[91] Covered T299,T300,T189
addr_hit[92] Covered T299,T300,T189
addr_hit[93] Covered T299,T300,T189
addr_hit[94] Covered T299,T300,T189
addr_hit[95] Covered T299,T300,T189
addr_hit[96] Covered T299,T300,T110
addr_hit[97] Covered T299,T300,T189
addr_hit[98] Covered T299,T300,T110
addr_hit[99] Covered T299,T300,T110
addr_hit[100] Covered T299,T300,T110
addr_hit[101] Covered T299,T300,T110
addr_hit[102] Covered T299,T300,T110
addr_hit[103] Covered T299,T300,T110
addr_hit[104] Covered T299,T300,T110
addr_hit[105] Covered T299,T300,T110
addr_hit[106] Covered T299,T300,T110
addr_hit[107] Covered T299,T300,T110
addr_hit[108] Covered T299,T300,T110
addr_hit[109] Covered T299,T300,T110
addr_hit[110] Covered T299,T300,T110
addr_hit[111] Covered T299,T300,T110
addr_hit[112] Covered T299,T300,T110
addr_hit[113] Covered T299,T300,T110
addr_hit[114] Covered T299,T300,T110
addr_hit[115] Covered T299,T300,T110
addr_hit[116] Covered T299,T300,T110
addr_hit[117] Covered T299,T300,T110
addr_hit[118] Covered T299,T300,T110
addr_hit[119] Covered T299,T300,T110
addr_hit[120] Covered T299,T300,T110
addr_hit[121] Covered T299,T300,T110
addr_hit[122] Covered T299,T300,T110
addr_hit[123] Covered T3,T65,T66
addr_hit[124] Covered T3,T65,T66
addr_hit[125] Covered T3,T65,T66
addr_hit[126] Covered T3,T65,T66
addr_hit[127] Covered T299,T300,T110
addr_hit[128] Covered T299,T300,T110
addr_hit[129] Covered T299,T300,T110
addr_hit[130] Covered T299,T300,T110
addr_hit[131] Covered T299,T300,T110
addr_hit[132] Covered T299,T300,T110
addr_hit[133] Covered T299,T300,T110
addr_hit[134] Covered T299,T300,T110
addr_hit[135] Covered T299,T300,T110
addr_hit[136] Covered T299,T300,T110
addr_hit[137] Covered T299,T300,T110
addr_hit[138] Covered T299,T300,T110
addr_hit[139] Covered T299,T300,T110
addr_hit[140] Covered T299,T300,T110
addr_hit[141] Covered T299,T300,T110
addr_hit[142] Covered T299,T300,T110
addr_hit[143] Covered T299,T300,T110
addr_hit[144] Covered T299,T300,T110
addr_hit[145] Covered T299,T300,T110
addr_hit[146] Covered T299,T300,T110
addr_hit[147] Covered T299,T300,T110
addr_hit[148] Covered T299,T300,T110
addr_hit[149] Covered T51,T52,T181
addr_hit[150] Covered T184,T299,T300
addr_hit[151] Covered T299,T300,T145
addr_hit[152] Covered T3,T65,T66
addr_hit[153] Covered T3,T65,T66
addr_hit[154] Covered T166,T299,T300
addr_hit[155] Covered T299,T300,T110
addr_hit[156] Covered T299,T300,T317
addr_hit[157] Covered T299,T300,T317
addr_hit[158] Covered T299,T300,T317
addr_hit[159] Covered T299,T300,T317
addr_hit[160] Covered T299,T300,T317
addr_hit[161] Covered T299,T300,T110
addr_hit[162] Covered T299,T300,T341
addr_hit[163] Covered T299,T300,T341
addr_hit[164] Covered T299,T300,T110
addr_hit[165] Covered T299,T300,T110
addr_hit[166] Covered T299,T300,T110
addr_hit[167] Covered T299,T300,T110
addr_hit[168] Covered T104,T299,T300
addr_hit[169] Covered T299,T300,T110
addr_hit[170] Covered T299,T300,T110
addr_hit[171] Covered T154,T299,T300
addr_hit[172] Covered T299,T300,T110
addr_hit[173] Covered T299,T300,T110
addr_hit[174] Covered T299,T300,T110
addr_hit[175] Covered T299,T300,T110
addr_hit[176] Covered T299,T300,T110
addr_hit[177] Covered T299,T300,T110
addr_hit[178] Covered T154,T299,T300
addr_hit[179] Covered T299,T300,T110
addr_hit[180] Covered T154,T299,T300
addr_hit[181] Covered T299,T300,T110
addr_hit[182] Covered T57,T171,T359
addr_hit[183] Covered T57,T171,T359
addr_hit[184] Covered T57,T171,T359
addr_hit[185] Covered T57,T171,T359
addr_hit[186] Covered T681,T682,T683
addr_hit[187] Covered T57,T171,T359
addr_hit[188] Covered T191,T151,T178
addr_hit[189] Covered T12,T299,T13
addr_hit[190] Covered T12,T299,T300
addr_hit[191] Covered T3,T65,T66
addr_hit[192] Covered T3,T51,T52
addr_hit[193] Covered T104,T154,T299
addr_hit[194] Covered T3,T51,T52
addr_hit[195] Covered T51,T52,T65
addr_hit[196] Covered T242,T243,T244
addr_hit[197] Covered T53,T54,T55
default Covered T75,T79,T107


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 476455720 221136 0 0
reAfterRv 476455720 221136 0 0
rePulse 476455720 153838 0 0
wePulse 476455720 67298 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 476455720 221136 0 0
T3 224354 40 0 0
T4 605918 0 0 0
T12 0 228 0 0
T29 166534 0 0 0
T39 700521 0 0 0
T40 705530 0 0 0
T41 663011 0 0 0
T51 127175 8 0 0
T52 144050 8 0 0
T65 0 44 0 0
T66 0 44 0 0
T85 89510 0 0 0
T86 111675 0 0 0
T144 0 44 0 0
T166 0 24 0 0
T191 0 51 0 0
T282 0 44 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 476455720 221136 0 0
T3 224354 40 0 0
T4 605918 0 0 0
T12 0 228 0 0
T29 166534 0 0 0
T39 700521 0 0 0
T40 705530 0 0 0
T41 663011 0 0 0
T51 127175 8 0 0
T52 144050 8 0 0
T65 0 44 0 0
T66 0 44 0 0
T85 89510 0 0 0
T86 111675 0 0 0
T144 0 44 0 0
T166 0 24 0 0
T191 0 51 0 0
T282 0 44 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 476455720 153838 0 0
T3 224354 12 0 0
T4 605918 0 0 0
T12 0 97 0 0
T29 166534 0 0 0
T39 700521 0 0 0
T40 705530 0 0 0
T41 663011 0 0 0
T51 127175 3 0 0
T52 144050 3 0 0
T65 0 14 0 0
T66 0 14 0 0
T85 89510 0 0 0
T86 111675 0 0 0
T144 0 14 0 0
T166 0 11 0 0
T191 0 21 0 0
T282 0 14 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 476455720 67298 0 0
T3 224354 28 0 0
T4 605918 0 0 0
T12 0 131 0 0
T29 166534 0 0 0
T39 700521 0 0 0
T40 705530 0 0 0
T41 663011 0 0 0
T51 127175 5 0 0
T52 144050 5 0 0
T65 0 30 0 0
T66 0 30 0 0
T85 89510 0 0 0
T86 111675 0 0 0
T144 0 30 0 0
T166 0 13 0 0
T191 0 30 0 0
T282 0 30 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%