Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T57,*T76	Yes	T75,T57,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	INPUT
tl_i.a_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_o.a_ready	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T40,T36,T191	Yes	T40,T36,T191	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T40,T36,T191	Yes	T39,T4,T40	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T40,T36,T191	Yes	T39,T4,T40	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T40,*T36,*T191	Yes	T40,T36,T191	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T66,T333,T666	Yes	T66,T333,T666	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T666,T673,T114	Yes	T114,T82,T118	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T114,T82,T118	Yes	T666,T673,T114	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T66,T333,T666	Yes	T66,T333,T666	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T36,T191,T151	Yes	T36,T191,T151	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T191,T151,T178	Yes	T191,T151,T178	OUTPUT
intr_rx_watermark_o	Yes	Yes	T191,T151,T178	Yes	T191,T151,T178	OUTPUT
intr_tx_empty_o	Yes	Yes	T191,T151,T178	Yes	T191,T151,T178	OUTPUT
intr_rx_overflow_o	Yes	Yes	T191,T151,T178	Yes	T191,T151,T178	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_break_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_timeout_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T57,*T76	Yes	T75,T57,T76	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	INPUT
tl_i.a_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_o.a_ready	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_o.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T40,T36,T191	Yes	T40,T36,T191	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T40,T36,T191	Yes	T39,T4,T40	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T40,T36,T191	Yes	T39,T4,T40	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T107,*T80	Yes	T75,T79,T107	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T40,*T36,*T191	Yes	T40,T36,T191	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T236,T237,T122	Yes	T236,T237,T122	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T236,T237,T122	Yes	T236,T237,T122	OUTPUT
cio_rx_i	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T36,T191,T37	Yes	T36,T191,T37	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T191,T299,T300	Yes	T191,T299,T300	OUTPUT
intr_rx_watermark_o	Yes	Yes	T191,T299,T300	Yes	T191,T299,T300	OUTPUT
intr_tx_empty_o	Yes	Yes	T191,T299,T300	Yes	T191,T299,T300	OUTPUT
intr_rx_overflow_o	Yes	Yes	T191,T299,T300	Yes	T191,T299,T300	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_break_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_timeout_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T57,*T76	Yes	T75,T57,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	INPUT
tl_i.a_valid	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	INPUT
tl_o.a_ready	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T76,*T80	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T151,*T187,*T188	Yes	T151,T187,T188	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T333,T236,T665	Yes	T333,T236,T665	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T673,T114,T291	Yes	T114,T82,T118	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T114,T82,T118	Yes	T673,T114,T291	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T333,T236,T665	Yes	T333,T236,T665	OUTPUT
cio_rx_i	Yes	Yes	T151,T187,T30	Yes	T151,T187,T30	INPUT
cio_tx_o	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
intr_rx_watermark_o	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
intr_tx_empty_o	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
intr_rx_overflow_o	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_break_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_timeout_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T57,*T76	Yes	T75,T57,T76	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	INPUT
tl_i.a_valid	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	INPUT
tl_o.a_ready	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T178,*T299,*T300	Yes	T178,T299,T300	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T666,T236,T237	Yes	T666,T236,T237	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T666,T82,T118	Yes	T82,T118,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T118,T83	Yes	T666,T82,T118	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T666,T236,T237	Yes	T666,T236,T237	OUTPUT
cio_rx_i	Yes	Yes	T178,T179,T347	Yes	T178,T179,T347	INPUT
cio_tx_o	Yes	Yes	T178,T179,T347	Yes	T178,T179,T347	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
intr_rx_watermark_o	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
intr_tx_empty_o	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
intr_rx_overflow_o	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_break_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_timeout_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T57,*T76	Yes	T75,T57,T76	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	INPUT
tl_i.a_valid	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	INPUT
tl_o.a_ready	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
tl_o.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T79,T107	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T107,*T80	Yes	T75,T79,T107	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T299,*T13,*T300	Yes	T299,T13,T300	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T66,T236,T667	Yes	T66,T236,T667	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T66,T236,T667	Yes	T66,T236,T667	OUTPUT
cio_rx_i	Yes	Yes	T13,T313,T328	Yes	T13,T313,T328	INPUT
cio_tx_o	Yes	Yes	T13,T313,T328	Yes	T13,T313,T328	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
intr_rx_watermark_o	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
intr_tx_empty_o	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
intr_rx_overflow_o	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_break_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_timeout_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T299,T300,T311	Yes	T299,T300,T311	OUTPUT

*Tests covering at least one bit in the range