Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T76,T107,T157	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T75,T80,T241	Yes	T75,T80,T241	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T3,T66,T144	Yes	T3,T66,T144	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T66,T144	Yes	T3,T66,T144	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T48,T76,T79	Yes	T48,T76,T79	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T48,T75,T57	Yes	T48,T75,T57	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T3,T66,T144	Yes	T3,T66,T144	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T3,T4,T29	Yes	T1,T3,T51	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T4,T71,T176	Yes	T4,T71,T176	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T29	Yes	T1,T3,T51	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T29	Yes	T1,T3,T51	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T4,T71,T176	Yes	T4,T71,T176	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T3,T4,T29	Yes	T1,T3,T51	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T4,T71,T176	Yes	T4,T71,T176	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T4,T71,T176	Yes	T4,T71,T176	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T71,T176	Yes	T4,T71,T176	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T4,T71,T176	Yes	T4,T71,T176	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T4,*T71,*T176	Yes	T4,T71,T176	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T4,T71,T176	Yes	T4,T71,T176	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T45,T75,T57	Yes	T45,T75,T57	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T48,T75	Yes	T45,T48,T75	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T45,T48,T75	Yes	T45,T48,T75	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T45,T75,T79	Yes	T45,T75,T79	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T45,T48,T75	Yes	T45,T48,T75	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T45,*T48,T75	Yes	T45,T48,T75	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T45,T48,T75	Yes	T45,T48,T75	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T45,T48,T57	Yes	T45,T48,T75	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T48,T75	Yes	T45,T48,T75	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T45,T48,T75	Yes	T45,T48,T75	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T45,*T48,T75	Yes	T45,T48,T75	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T45,*T48,*T75	Yes	T45,T48,T75	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T45,T48,T75	Yes	T45,T48,T75	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T195,T196,T45	Yes	T195,T196,T45	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T195,T196,T45	Yes	T195,T196,T45	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T195,T196,T45	Yes	T195,T196,T45	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T195,T196,T45	Yes	T195,T196,T45	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T195,T196,T45	Yes	T195,T196,T45	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T195,*T196,*T197	Yes	T195,T196,T197	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T195,T196,T45	Yes	T195,T196,T45	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T3,T51	Yes	T1,T3,T51	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T3,T51	Yes	T3,T4,T29	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T195,T196,T197	Yes	T195,T196,T197	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T195,T196,T45	Yes	T195,T196,T45	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T3,T51	Yes	T3,T4,T29	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T197	Yes	T195,T196,T197	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T51	Yes	T3,T4,T29	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T195,T196,T45	Yes	T195,T196,T45	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T2,T39,T4	Yes	T2,T39,T4	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T71,T407,T258	Yes	T71,T407,T258	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T53,T45,T48	Yes	T53,T45,T48	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T408,T263	Yes	T5,T408,T263	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T5,T408,T263	Yes	T5,T408,T263	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T53,T45,T48	Yes	T53,T45,T48	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T5,T408,T263	Yes	T5,T408,T263	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T45,*T48,T75	Yes	T45,T48,T75	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T5,T408,T263	Yes	T5,T408,T263	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T5,T408,T263	Yes	T5,T408,T263	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T5,T408,T263	Yes	T5,T408,T263	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T48,T75	Yes	T53,T45,T48	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T5,T408,T263	Yes	T5,T408,T263	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T45,*T48,T75	Yes	T45,T48,T75	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T5,*T263,*T409	Yes	T5,T408,T263	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T5,T408,T263	Yes	T5,T408,T263	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T119,T265,T266	Yes	T119,T265,T266	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T386,T110,T236	Yes	T386,T110,T236	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T110,T236,T237	Yes	T110,T236,T237	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T386,T110,T236	Yes	T386,T110,T236	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T386,T110,T236	Yes	T386,T110,T236	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T110,T236,T237	Yes	T110,T236,T237	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T386,T110,T236	Yes	T386,T110,T236	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T75,*T79,*T107	Yes	T75,T79,T107	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T182,T183	Yes	T10,T182,T183	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T386,T110,T236	Yes	T386,T110,T236	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T386,T110,T236	Yes	T386,T110,T236	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T75,T79,T80	Yes	T75,T79,T80	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T110,T111,T112	Yes	T110,T111,T112	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T386,T110,T236	Yes	T386,T110,T236	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T110,T111,T112	Yes	T110,T111,T112	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T75,T79,T80	Yes	T75,T79,T107	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T75,*T80,*T157	Yes	T75,T79,T107	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T107	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T386,*T110,*T111	Yes	T386,T110,T111	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T386,T110,T236	Yes	T386,T110,T236	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T30,T31,T386	Yes	T30,T31,T386	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T30,T31,T110	Yes	T30,T31,T110	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T30,T31,T386	Yes	T30,T31,T386	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T30,T31,T386	Yes	T30,T31,T386	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T30,T31,T110	Yes	T30,T31,T110	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T30,T31,T386	Yes	T30,T31,T386	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T75,*T79,*T107	Yes	T75,T79,T107	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T30,T31,T386	Yes	T30,T31,T386	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T30,T31,T386	Yes	T30,T31,T386	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T79,T107	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T30,T31,T110	Yes	T30,T31,T110	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T31,T386	Yes	T30,T31,T386	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T30,T31,T110	Yes	T30,T31,T110	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T75,*T80,*T157	Yes	T75,T79,T107	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T76	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T30,*T31,*T386	Yes	T30,T31,T386	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T30,T31,T386	Yes	T30,T31,T386	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T299,T300,T16	Yes	T299,T300,T16	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T75,*T79,*T107	Yes	T75,T79,T107	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	INPUT
tl_usbdev_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T107,T80	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T107,T80	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T75,*T80,*T157	Yes	T75,T107,T80	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T107	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T177,*T299,*T300	Yes	T177,T299,T300	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T177,T299,T300	Yes	T177,T299,T300	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T39	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T75,T76,T107	Yes	T75,T79,T107	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T45,T207,T75	Yes	T45,T207,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T207,T75	Yes	T45,T207,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T45,T207,T75	Yes	T45,T207,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T45,T207,T75	Yes	T45,T207,T75	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T45,T207,T75	Yes	T45,T207,T75	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T45,*T207,T75	Yes	T45,T207,T75	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T45,T207,T75	Yes	T45,T207,T75	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T45,T207,T57	Yes	T45,T207,T75	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T75,T79,T80	Yes	T75,T79,T107	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T45,T207,T75	Yes	T45,T207,T75	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T207,T75	Yes	T45,T207,T75	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T45,T207,T75	Yes	T45,T207,T75	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T45,*T207,T75	Yes	T45,T207,T75	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T45,T207,T75	Yes	T45,T207,T75	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T2,T3,T39	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T341,T342,T694	Yes	T341,T342,T694	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_hmac_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_hmac_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T79,T107	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T39,*T4,*T40	Yes	T39,T4,T40	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_kmac_o.d_ready	Yes	Yes	T2,T3,T86	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T86,T419,T220	Yes	T86,T419,T220	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T86,T109,T134	Yes	T86,T109,T134	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T86,T109,T134	Yes	T86,T109,T134	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T86,T419,T220	Yes	T86,T419,T220	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T86,T109,T134	Yes	T86,T109,T134	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T86,T419,T420	Yes	T86,T419,T420	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T86,T109,T134	Yes	T86,T109,T134	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T86,T109,T134	Yes	T86,T109,T134	INPUT
tl_kmac_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T86,T109,T134	Yes	T86,T109,T134	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T86,T109,T134	Yes	T86,T109,T134	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T86,T109,T134	Yes	T86,T134,T419	INPUT
tl_kmac_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T86,*T109,*T134	Yes	T86,T134,T419	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T86,T109,T134	Yes	T86,T109,T134	INPUT
tl_aes_o.d_ready	Yes	Yes	T2,T3,T85	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T85,T366,T109	Yes	T85,T366,T109	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T85,T366,T109	Yes	T85,T366,T109	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T85,T366,T109	Yes	T85,T366,T109	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T85,T366,T109	Yes	T85,T366,T109	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T85,T366,T109	Yes	T85,T366,T109	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T48,*T207,*T75	Yes	T48,T207,T75	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T107	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T75,T57,T80	Yes	T75,T57,T80	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T85,T366,T109	Yes	T85,T366,T109	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T85,T366,T109	Yes	T85,T366,T109	INPUT
tl_aes_i.d_error	Yes	Yes	T75,T79,T80	Yes	T75,T79,T80	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T85,T366,T109	Yes	T85,T366,T109	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T366,T109	Yes	T85,T366,T109	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T85,T366,T282	Yes	T85,T366,T109	INPUT
tl_aes_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T80,T241	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T48,*T207,*T75	Yes	T48,T207,T75	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T75,T57,T80	Yes	T75,T57,T80	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T85,*T366,*T109	Yes	T85,T366,T109	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T85,T366,T109	Yes	T85,T366,T109	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T75,T79,T80	Yes	T75,T79,T80	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T39	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T2,T3,T39	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T75,T79,T80	Yes	T75,T79,T107	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T109,*T104,*T154	Yes	T39,T40,T41	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T45,*T48,*T207	Yes	T45,T48,T207	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T76,T79	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T45,*T48,*T207	Yes	T45,T48,T207	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T109,*T104,*T154	Yes	T109,T104,T154	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T79,T107	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T107,T80	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T109,*T104,*T154	Yes	T109,T104,T154	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T107	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	INPUT
tl_edn1_i.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	INPUT
tl_edn1_i.d_sink	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T107	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T109,*T104,*T154	Yes	T109,T104,T154	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T109,T104,T154	Yes	T109,T104,T154	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T2,T3,T51	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T75,*T79,*T80	Yes	T75,T79,T80	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T65,T66	Yes	T3,T65,T66	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T75,T107,T80	Yes	T75,T79,T107	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T75,*T80,*T157	Yes	T75,T79,T80	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T3,*T51,*T52	Yes	T3,T51,T52	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	INPUT
tl_otbn_o.d_ready	Yes	Yes	T2,T3,T39	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T71,*T78,*T412	Yes	T71,T78,T412	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_otbn_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_otbn_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T71,*T78,*T412	Yes	T71,T78,T412	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T39,*T4,*T40	Yes	T39,T4,T40	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T2,T3,T39	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T109,T134,T135	Yes	T109,T134,T135	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_keymgr_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T109,T134,T135	Yes	T109,T134,T135	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T39,*T4,*T40	Yes	T39,T4,T40	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T45,*T48,*T75	Yes	T45,T48,T75	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T45,T48,T75	Yes	T45,T48,T75	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T45,*T48,*T75	Yes	T45,T48,T75	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T79	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T39	Yes	T1,T3,T39	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T2,T3,T39	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T131,T36,T139	Yes	T39,T4,T40	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T131,T36,T139	Yes	T39,T4,T40	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	T75,*T76,*T79	Yes	T75,T76,T79	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T131,*T139,*T140	Yes	T131,T411,T139	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range