Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T119,T265,T266	Yes	T119,T265,T266	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_uart0_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T76,T79	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T40,T36,T191	Yes	T40,T36,T191	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T40,T36,T191	Yes	T39,T4,T40	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T40,T36,T191	Yes	T39,T4,T40	INPUT
tl_uart0_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T76,T79	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T75,*T107,*T80	Yes	T75,T79,T107	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T40,*T36,*T191	Yes	T40,T36,T191	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	INPUT
tl_uart1_i.d_error	Yes	Yes	T75,T76,T80	Yes	T75,T76,T80	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	INPUT
tl_uart1_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T80	Yes	T75,T76,T79	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T151,*T187,*T188	Yes	T151,T187,T188	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T151,T187,T188	Yes	T151,T187,T188	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	INPUT
tl_uart2_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	INPUT
tl_uart2_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T178,*T299,*T300	Yes	T178,T299,T300	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T178,T299,T300	Yes	T178,T299,T300	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	INPUT
tl_uart3_i.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T79,T107	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	INPUT
tl_uart3_i.d_sink	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T75,*T107,*T80	Yes	T75,T79,T107	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T79	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T299,*T13,*T300	Yes	T299,T13,T300	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T299,T13,T300	Yes	T299,T13,T300	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T185,T186,T324	Yes	T185,T186,T324	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T185,T186,T324	Yes	T185,T186,T324	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T236,T185,T186	Yes	T236,T185,T186	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T236,T185,T186	Yes	T236,T185,T186	INPUT
tl_i2c0_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T185,T186,T324	Yes	T185,T186,T324	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T236,T185,T186	Yes	T236,T185,T186	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T236,T185,T186	Yes	T236,T185,T186	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T185,*T186,*T324	Yes	T185,T186,T324	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T236,T185,T186	Yes	T236,T185,T186	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T189,T319,T95	Yes	T189,T319,T95	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T189,T319,T95	Yes	T189,T319,T95	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T189,T319,T95	Yes	T189,T319,T95	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T189,T319,T95	Yes	T189,T319,T95	INPUT
tl_i2c1_i.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T189,T319,T95	Yes	T189,T319,T95	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T189,T319,T95	Yes	T189,T319,T95	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T189,T319,T95	Yes	T189,T319,T95	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T107	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T189,*T319,*T95	Yes	T189,T319,T95	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T189,T319,T95	Yes	T189,T319,T95	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T326,T695,T696	Yes	T326,T695,T696	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T326,T695,T696	Yes	T326,T695,T696	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T236,T237,T326	Yes	T236,T237,T326	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T236,T237,T326	Yes	T236,T237,T326	INPUT
tl_i2c2_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T326,T312,T323	Yes	T326,T312,T323	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T236,T237,T326	Yes	T236,T237,T326	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T236,T237,T326	Yes	T236,T237,T326	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T75,T76,T107	Yes	T75,T76,T79	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T326,*T695,*T696	Yes	T326,T695,T696	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T236,T237,T326	Yes	T236,T237,T326	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T110,T111,T112	Yes	T110,T111,T112	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T110,T111,T112	Yes	T110,T111,T112	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T110,T111,T112	Yes	T110,T111,T112	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T110,T111,T112	Yes	T110,T111,T112	INPUT
tl_pattgen_i.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T110,T111,T112	Yes	T110,T111,T112	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T110,T111,T112	Yes	T110,T111,T112	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T110,T111,T112	Yes	T110,T111,T112	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T75,T107,T80	Yes	T75,T79,T107	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T75,T80,T157	Yes	T75,T79,T107	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T107	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T110,*T111,*T112	Yes	T110,T111,T112	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T110,T111,T112	Yes	T110,T111,T112	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T190,T90,T180	Yes	T190,T90,T180	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T190,T90,T180	Yes	T190,T90,T180	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T190,T90,T180	Yes	T190,T90,T180	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T190,T90,T180	Yes	T190,T90,T180	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T107	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T190,T90,T180	Yes	T190,T90,T180	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T190,T90,T180	Yes	T190,T90,T180	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T190,T90,T180	Yes	T190,T90,T180	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T107	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T45,*T48,T75	Yes	T45,T48,T75	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T190,*T90,*T180	Yes	T190,T90,T180	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T190,T90,T180	Yes	T190,T90,T180	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T39,T41,T36	Yes	T39,T41,T36	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	INPUT
tl_gpio_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T12,T23,T24	Yes	T12,T23,T24	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T12,T23,T24	Yes	T12,T180,T14	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T12,T23,T24	Yes	T12,T180,T14	INPUT
tl_gpio_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T80	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T45,*T207,*T75	Yes	T45,T207,T75	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T3,*T29,*T65	Yes	T1,T3,T39	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T77,T110,T169	Yes	T77,T110,T169	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T77,T110,T169	Yes	T77,T110,T169	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T77,T110,T169	Yes	T77,T110,T169	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T77,T110,T169	Yes	T77,T110,T169	INPUT
tl_spi_device_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T79,T107	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T77,T110,T169	Yes	T77,T110,T169	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T77,T110,T169	Yes	T77,T110,T169	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T77,T110,T169	Yes	T77,T110,T169	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T75,*T107,*T80	Yes	T75,T79,T107	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T79	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T77,*T110,*T169	Yes	T77,T110,T169	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T77,T110,T169	Yes	T77,T110,T169	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T245,T248,T100	Yes	T245,T248,T100	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T245,T248,T100	Yes	T245,T248,T100	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T245,T248,T100	Yes	T245,T248,T100	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T245,T248,T100	Yes	T245,T248,T100	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T245,T248,T100	Yes	T245,T248,T100	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T245,T248,T100	Yes	T245,T248,T100	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T245,T248,T100	Yes	T245,T248,T100	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T75,*T79,*T107	Yes	T75,T79,T107	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T245,*T248,*T100	Yes	T245,T248,T100	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T245,T248,T100	Yes	T245,T248,T100	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T39,T51,T52	Yes	T39,T51,T52	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T39,T51,T52	Yes	T39,T51,T52	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T39,T51,T52	Yes	T39,T51,T52	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T39,T51,T52	Yes	T39,T51,T52	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T51,T52,T177	Yes	T51,T52,T177	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T51,T52	Yes	T39,T51,T52	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T39,T51,T52	Yes	T39,T51,T52	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T45,*T48,*T75	Yes	T45,T48,T75	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T76	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T39,*T51,*T52	Yes	T39,T51,T52	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T39,T51,T52	Yes	T39,T51,T52	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T75,T80,T241	Yes	T75,T80,T241	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T39,T4	Yes	T1,T3,T39	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T3,T39,T4	Yes	T1,T3,T39	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T45,*T48,*T75	Yes	T45,T48,T75	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T39	Yes	T1,T3,T39	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T3,T39	Yes	T1,T3,T39	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T366,T191	Yes	T4,T366,T191	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T86,T4,T366	Yes	T86,T4,T366	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T366,T191,T335	Yes	T4,T366,T191	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T48,*T207,*T75	Yes	T4,T108,T702	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T366,*T191,*T335	Yes	T4,T366,T191	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T75,T79,T80	Yes	T75,T79,T80	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T75,T79,T80	Yes	T75,T79,T80	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T45,*T48,*T75	Yes	T45,T48,T75	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T4,*T77,*T108	Yes	T4,T77,T108	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T29,*T109	Yes	T4,T29,T109	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T3,T51	Yes	T1,T3,T51	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T3,T51	Yes	T3,T4,T29	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T3,T51	Yes	T3,T4,T29	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T51	Yes	T3,T4,T29	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T79,T107	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T62,T63,T133	Yes	T62,T63,T133	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T76,T79	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T195,*T196,*T197	Yes	T195,T196,T197	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T5,*T36,*T134	Yes	T39,T4,T40	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T166,T123,T158	Yes	T166,T123,T158	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T166,T123,T158	Yes	T166,T123,T158	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T75,*T80,*T157	Yes	T75,T79,T107	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T79	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T29	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T75,T79,T80	Yes	T75,T80,T241	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T75,T76,T80	Yes	T75,T79,T107	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T48,*T207,*T75	Yes	T48,T207,T75	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T75,T57,T80	Yes	T75,T57,T76	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T3,*T51,*T52	Yes	T3,T39,T51	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T75,T80,T241	Yes	T75,T80,T241	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T131,T139,T140	Yes	T131,T139,T140	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T131,T36,T139	Yes	T39,T4,T40	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T131,T36,T139	Yes	T39,T4,T40	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T75,*T80,*T157	Yes	T75,T107,T80	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T107	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T131,*T139,*T140	Yes	T131,T411,T139	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T39,T4,T40	Yes	T39,T4,T40	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T39	Yes	T2,T3,T39	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T39	Yes	T2,T3,T39	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T39	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T2,T3,T39	Yes	T2,T3,T39	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T71,*T78,*T412	Yes	T71,T78,T412	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T39	Yes	T1,T3,T39	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T75,T80,T241	Yes	T75,T107,T80	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T51,T52	Yes	T3,T51,T52	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T107,T80	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T48,*T207,*T75	Yes	T48,T207,T75	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T107	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T3,*T39,*T51	Yes	T3,T39,T51	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T3,T39,T51	Yes	T3,T39,T51	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T29,T124,T184	Yes	T29,T124,T184	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T29,T124,T184	Yes	T29,T124,T184	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T29,T124,T184	Yes	T29,T124,T184	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T29,T124,T184	Yes	T29,T124,T184	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T79,T107,T80	Yes	T79,T107,T80	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T124,T184,T299	Yes	T124,T184,T299	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T124,T184	Yes	T29,T124,T184	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T29,T124,T184	Yes	T29,T124,T184	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T75,*T79,*T80	Yes	T75,T79,T107	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T79	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T124,*T184,*T299	Yes	T29,T124,T184	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T29,T124,T184	Yes	T29,T124,T184	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T29,T145,T146	Yes	T29,T145,T146	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T29,T145,T146	Yes	T29,T145,T146	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T29,T145,T146	Yes	T29,T145,T146	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T29,T145,T146	Yes	T29,T145,T146	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T145,T146,T312	Yes	T29,T145,T146	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T145,T146	Yes	T29,T145,T146	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T29,T145,T146	Yes	T29,T145,T146	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T79,T107	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T48,*T207,T75	Yes	T48,T207,T75	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T57,T79	Yes	T75,T57,T79	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T145,*T146,*T147	Yes	T29,T145,T146	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T29,T145,T146	Yes	T29,T145,T146	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T4,*T71,*T77	Yes	T4,T71,T77	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T75,T57,T76	Yes	T75,T57,T76	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T71,T78,T45	Yes	T71,T78,T45	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T75,T107,T80	Yes	T75,T107,T80	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T107	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T2,T3,T29	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T75,T79,T107	Yes	T75,T107,T80	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T75,*T80,*T157	Yes	T75,T107,T80	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T75,T57,T107	Yes	T75,T57,T107	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T75,*T57,*T79	Yes	T75,T57,T107	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range