Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T143,T292,T293
0	1	Covered	T143,T292,T293
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T143,T292,T293
1	Covered	T143,T292,T293

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T143,T292,T293
1	Covered	T143,T292,T293

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T143,T292,T293
1	1	Covered	T143,T292,T293

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T143,T292,T293
1	0	Covered	T143,T292,T293
1	1	Covered	T143,T292,T293

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T143,T292,T293

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T143,T292,T293
0	Covered	T143,T292,T293

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T143,T292,T293
0	Covered	T143,T292,T293

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	801084908	780758592	0	0
CheckNGreaterZero_A	1906	1906	0	0
GntImpliesReady_A	801084908	5346	0	0
GntImpliesValid_A	801084908	5346	0	0
GrantKnown_A	801084908	780758592	0	0
IdxKnown_A	801084908	780758592	0	0
IndexIsCorrect_A	801084908	5346	0	0
NoReadyValidNoGrant_A	801084908	0	0	0
Priority_A	801084908	5346	0	0
ReadyAndValidImplyGrant_A	801084908	5346	0	0
ReqAndReadyImplyGrant_A	801084908	5346	0	0
ReqImpliesValid_A	801084908	5346	0	0
ValidKnown_A	801084908	780758592	0	0
gen_data_port_assertion.DataFlow_A	801084908	5346	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	780758592	0	0
T1	172544	172442	0	0
T2	1631308	1630076	0	0
T3	448708	448482	0	0
T4	1211836	1211500	0	0
T39	1401042	1400940	0	0
T40	1411060	1410944	0	0
T51	254350	254234	0	0
T52	288100	287984	0	0
T85	179020	178918	0	0
T86	223350	223248	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1906	1906	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T39	2	2	0	0
T40	2	2	0	0
T51	2	2	0	0
T52	2	2	0	0
T85	2	2	0	0
T86	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	5346	0	0
T46	365306	0	0	0
T143	154676	1783	0	0
T288	650794	0	0	0
T289	252972	0	0	0
T290	268820	0	0	0
T291	311426	0	0	0
T292	0	1784	0	0
T293	0	1779	0	0
T315	399930	0	0	0
T381	410656	0	0	0
T382	384548	0	0	0
T383	252776	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	5346	0	0
T46	365306	0	0	0
T143	154676	1783	0	0
T288	650794	0	0	0
T289	252972	0	0	0
T290	268820	0	0	0
T291	311426	0	0	0
T292	0	1784	0	0
T293	0	1779	0	0
T315	399930	0	0	0
T381	410656	0	0	0
T382	384548	0	0	0
T383	252776	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	780758592	0	0
T1	172544	172442	0	0
T2	1631308	1630076	0	0
T3	448708	448482	0	0
T4	1211836	1211500	0	0
T39	1401042	1400940	0	0
T40	1411060	1410944	0	0
T51	254350	254234	0	0
T52	288100	287984	0	0
T85	179020	178918	0	0
T86	223350	223248	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	780758592	0	0
T1	172544	172442	0	0
T2	1631308	1630076	0	0
T3	448708	448482	0	0
T4	1211836	1211500	0	0
T39	1401042	1400940	0	0
T40	1411060	1410944	0	0
T51	254350	254234	0	0
T52	288100	287984	0	0
T85	179020	178918	0	0
T86	223350	223248	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	5346	0	0
T46	365306	0	0	0
T143	154676	1783	0	0
T288	650794	0	0	0
T289	252972	0	0	0
T290	268820	0	0	0
T291	311426	0	0	0
T292	0	1784	0	0
T293	0	1779	0	0
T315	399930	0	0	0
T381	410656	0	0	0
T382	384548	0	0	0
T383	252776	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	5346	0	0
T46	365306	0	0	0
T143	154676	1783	0	0
T288	650794	0	0	0
T289	252972	0	0	0
T290	268820	0	0	0
T291	311426	0	0	0
T292	0	1784	0	0
T293	0	1779	0	0
T315	399930	0	0	0
T381	410656	0	0	0
T382	384548	0	0	0
T383	252776	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	5346	0	0
T46	365306	0	0	0
T143	154676	1783	0	0
T288	650794	0	0	0
T289	252972	0	0	0
T290	268820	0	0	0
T291	311426	0	0	0
T292	0	1784	0	0
T293	0	1779	0	0
T315	399930	0	0	0
T381	410656	0	0	0
T382	384548	0	0	0
T383	252776	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	5346	0	0
T46	365306	0	0	0
T143	154676	1783	0	0
T288	650794	0	0	0
T289	252972	0	0	0
T290	268820	0	0	0
T291	311426	0	0	0
T292	0	1784	0	0
T293	0	1779	0	0
T315	399930	0	0	0
T381	410656	0	0	0
T382	384548	0	0	0
T383	252776	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	5346	0	0
T46	365306	0	0	0
T143	154676	1783	0	0
T288	650794	0	0	0
T289	252972	0	0	0
T290	268820	0	0	0
T291	311426	0	0	0
T292	0	1784	0	0
T293	0	1779	0	0
T315	399930	0	0	0
T381	410656	0	0	0
T382	384548	0	0	0
T383	252776	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	780758592	0	0
T1	172544	172442	0	0
T2	1631308	1630076	0	0
T3	448708	448482	0	0
T4	1211836	1211500	0	0
T39	1401042	1400940	0	0
T40	1411060	1410944	0	0
T51	254350	254234	0	0
T52	288100	287984	0	0
T85	179020	178918	0	0
T86	223350	223248	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801084908	5346	0	0
T46	365306	0	0	0
T143	154676	1783	0	0
T288	650794	0	0	0
T289	252972	0	0	0
T290	268820	0	0	0
T291	311426	0	0	0
T292	0	1784	0	0
T293	0	1779	0	0
T315	399930	0	0	0
T381	410656	0	0	0
T382	384548	0	0	0
T383	252776	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T143,T292,T293
0	1	Covered	T143,T292,T293
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T143,T292,T293
1	Covered	T143,T292,T293

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T143,T292,T293
1	Covered	T143,T292,T293

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T143,T292,T293
1	1	Covered	T143,T292,T293

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T143,T292,T293
1	0	Covered	T143,T292,T293
1	1	Covered	T143,T292,T293

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T143,T292,T293

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T143,T292,T293
0	Covered	T143,T292,T293

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T143,T292,T293
0	Covered	T143,T292,T293

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400542454	390379296	0	0
CheckNGreaterZero_A	953	953	0	0
GntImpliesReady_A	400542454	4314	0	0
GntImpliesValid_A	400542454	4314	0	0
GrantKnown_A	400542454	390379296	0	0
IdxKnown_A	400542454	390379296	0	0
IndexIsCorrect_A	400542454	4314	0	0
NoReadyValidNoGrant_A	400542454	0	0	0
Priority_A	400542454	4314	0	0
ReadyAndValidImplyGrant_A	400542454	4314	0	0
ReqAndReadyImplyGrant_A	400542454	4314	0	0
ReqImpliesValid_A	400542454	4314	0	0
ValidKnown_A	400542454	390379296	0	0
gen_data_port_assertion.DataFlow_A	400542454	4314	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	390379296	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	953	953	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	4314	0	0
T46	182653	0	0	0
T143	77338	1439	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	1440	0	0
T293	0	1435	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	4314	0	0
T46	182653	0	0	0
T143	77338	1439	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	1440	0	0
T293	0	1435	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	390379296	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	390379296	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	4314	0	0
T46	182653	0	0	0
T143	77338	1439	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	1440	0	0
T293	0	1435	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	4314	0	0
T46	182653	0	0	0
T143	77338	1439	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	1440	0	0
T293	0	1435	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	4314	0	0
T46	182653	0	0	0
T143	77338	1439	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	1440	0	0
T293	0	1435	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	4314	0	0
T46	182653	0	0	0
T143	77338	1439	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	1440	0	0
T293	0	1435	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	4314	0	0
T46	182653	0	0	0
T143	77338	1439	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	1440	0	0
T293	0	1435	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	390379296	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	4314	0	0
T46	182653	0	0	0
T143	77338	1439	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	1440	0	0
T293	0	1435	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T143,T292,T293
0	1	Covered	T143,T292,T293
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T143,T292,T293
1	Covered	T143,T292,T293

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T143,T292,T293
1	Covered	T143,T292,T293

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T143,T292,T293
1	1	Covered	T143,T292,T293

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T143,T292,T293
1	0	Covered	T143,T292,T293
1	1	Covered	T143,T292,T293

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T143,T292,T293

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T143,T292,T293
0	Covered	T143,T292,T293

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T143,T292,T293
0	Covered	T143,T292,T293

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400542454	390379296	0	0
CheckNGreaterZero_A	953	953	0	0
GntImpliesReady_A	400542454	1032	0	0
GntImpliesValid_A	400542454	1032	0	0
GrantKnown_A	400542454	390379296	0	0
IdxKnown_A	400542454	390379296	0	0
IndexIsCorrect_A	400542454	1032	0	0
NoReadyValidNoGrant_A	400542454	0	0	0
Priority_A	400542454	1032	0	0
ReadyAndValidImplyGrant_A	400542454	1032	0	0
ReqAndReadyImplyGrant_A	400542454	1032	0	0
ReqImpliesValid_A	400542454	1032	0	0
ValidKnown_A	400542454	390379296	0	0
gen_data_port_assertion.DataFlow_A	400542454	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	390379296	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	953	953	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	1032	0	0
T46	182653	0	0	0
T143	77338	344	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	344	0	0
T293	0	344	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	1032	0	0
T46	182653	0	0	0
T143	77338	344	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	344	0	0
T293	0	344	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	390379296	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	390379296	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	1032	0	0
T46	182653	0	0	0
T143	77338	344	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	344	0	0
T293	0	344	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	1032	0	0
T46	182653	0	0	0
T143	77338	344	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	344	0	0
T293	0	344	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	1032	0	0
T46	182653	0	0	0
T143	77338	344	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	344	0	0
T293	0	344	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	1032	0	0
T46	182653	0	0	0
T143	77338	344	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	344	0	0
T293	0	344	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	1032	0	0
T46	182653	0	0	0
T143	77338	344	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	344	0	0
T293	0	344	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	390379296	0	0
T1	86272	86221	0	0
T2	815654	815038	0	0
T3	224354	224241	0	0
T4	605918	605750	0	0
T39	700521	700470	0	0
T40	705530	705472	0	0
T51	127175	127117	0	0
T52	144050	143992	0	0
T85	89510	89459	0	0
T86	111675	111624	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400542454	1032	0	0
T46	182653	0	0	0
T143	77338	344	0	0
T288	325397	0	0	0
T289	126486	0	0	0
T290	134410	0	0	0
T291	155713	0	0	0
T292	0	344	0	0
T293	0	344	0	0
T315	199965	0	0	0
T381	205328	0	0	0
T382	192274	0	0	0
T383	126388	0	0	0