Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3894107	1			T69	92		T70	1436		T71	489
values[2]	782475	1			T69	43		T70	481		T71	44
values[3]	103223	1			T70	29		T71	29		T74	5
values[4]	53086	1			T70	1		T71	23		T74	2
values[5]	35266	1			T71	19		T222	33		T388	53
values[6]	27159	1			T71	19		T222	20		T388	44
values[7]	22104	1			T71	27		T222	15		T388	61
values[8]	19186	1			T71	25		T222	28		T388	51
values[9]	17171	1			T71	24		T222	7		T388	26
values[10]	15454	1			T71	32		T222	3		T388	40
values[11]	14437	1			T71	41		T222	6		T388	37
values[12]	13689	1			T71	32		T222	13		T388	32
values[13]	13215	1			T71	33		T222	14		T388	48
values[14]	12491	1			T71	17		T222	9		T388	41
values[15]	11763	1			T71	21		T222	11		T388	39
values[16]	11050	1			T71	15		T222	7		T388	23
values[17]	10904	1			T71	14		T222	2		T388	30
values[18]	10456	1			T71	13		T222	3		T388	38
values[19]	10076	1			T71	10		T222	1		T388	40
values[20]	10060	1			T71	12		T222	1		T388	29
values[21]	9432	1			T71	15		T222	1		T388	21
values[22]	9459	1			T71	23		T222	1		T388	28
values[23]	9116	1			T71	29		T222	1		T388	18
values[24]	8816	1			T71	21		T222	1		T388	26
values[25]	8069	1			T71	19		T222	8		T388	33
values[26]	7857	1			T71	29		T222	4		T388	35
values[27]	7426	1			T71	11		T222	1		T388	22
values[28]	7052	1			T71	3		T222	1		T388	12
values[29]	6878	1			T71	3		T222	1		T388	8
values[30]	6487	1			T71	7		T222	1		T388	7
values[31]	6144	1			T71	8		T222	2		T388	12
values[32]	5596	1			T71	5		T222	1		T388	15
values[33]	5215	1			T71	5		T222	1		T388	21
values[34]	4704	1			T71	5		T222	2		T388	10
values[35]	4565	1			T71	4		T222	1		T388	15
values[36]	4386	1			T71	5		T222	7		T388	21
values[37]	4134	1			T71	4		T222	1		T388	26
values[38]	3828	1			T71	2		T222	5		T388	11
values[39]	3679	1			T71	4		T222	9		T388	7
values[40]	3652	1			T71	9		T222	5		T388	5
values[41]	3428	1			T71	2		T222	11		T388	4
values[42]	3327	1			T71	6		T222	4		T388	1
values[43]	3439	1			T71	4		T403	23		T802	1
values[44]	3422	1			T71	6		T403	19		T802	1
values[45]	3315	1			T71	3		T403	12		T802	1
values[46]	3268	1			T71	6		T403	9		T802	1
values[47]	3216	1			T71	5		T403	9		T802	1
values[48]	3054	1			T71	3		T403	10		T802	1
values[49]	3029	1			T71	2		T403	11		T802	1
values[50]	2965	1			T71	3		T403	18		T802	1
values[51]	2928	1			T71	6		T403	20		T802	1
values[52]	2842	1			T71	4		T403	21		T802	1
values[53]	2798	1			T71	5		T403	19		T802	1
values[54]	2788	1			T71	3		T403	19		T802	1
values[55]	2669	1			T71	6		T403	16		T802	1
values[56]	2605	1			T71	4		T403	18		T802	1
values[57]	2553	1			T71	5		T403	13		T802	1
values[58]	2506	1			T71	5		T403	17		T802	1
values[59]	2496	1			T71	3		T403	18		T802	1
values[60]	2511	1			T71	5		T403	11		T802	1
values[61]	2747	1			T403	11		T802	1		T817	2
values[62]	4183	1			T403	21		T802	1		T817	2
values[63]	16243	1			T403	83		T802	1		T817	45
values[64]	235903	1			T403	222		T802	210		T817	269

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4966237	1			T69	120		T70	1495		T71	930
values[2]	812625	1			T69	38		T70	428		T71	226
values[3]	79221	1			T69	2		T70	133		T71	11
values[4]	14283	1			T70	46		T71	1		T74	9
values[5]	5558	1			T70	12		T74	1		T222	3
values[6]	3365	1			T70	1		T222	2		T402	3
values[7]	2512	1			T222	2		T402	2		T403	17
values[8]	2048	1			T222	2		T402	2		T403	9
values[9]	1958	1			T222	2		T402	1		T403	23
values[10]	1795	1			T222	2		T402	1		T403	8
values[11]	1668	1			T222	2		T402	2		T403	3
values[12]	1589	1			T222	2		T402	3		T507	14
values[13]	1478	1			T222	2		T402	2		T507	16
values[14]	1262	1			T222	2		T402	2		T507	11
values[15]	1223	1			T222	2		T402	2		T507	10
values[16]	1194	1			T222	2		T402	2		T507	9
values[17]	1097	1			T222	2		T402	2		T507	13
values[18]	1031	1			T222	2		T402	2		T507	12
values[19]	929	1			T222	2		T402	2		T507	4
values[20]	879	1			T222	3		T402	1		T507	5
values[21]	940	1			T222	2		T402	1		T507	5
values[22]	881	1			T222	2		T402	2		T507	12
values[23]	878	1			T222	2		T402	1		T507	11
values[24]	767	1			T222	2		T402	1		T507	4
values[25]	732	1			T222	2		T402	2		T507	2
values[26]	665	1			T222	2		T402	4		T507	3
values[27]	702	1			T222	2		T402	2		T507	5
values[28]	736	1			T222	1		T402	2		T507	2
values[29]	654	1			T222	1		T402	2		T399	17
values[30]	629	1			T222	3		T402	2		T399	18
values[31]	607	1			T222	2		T402	2		T399	16
values[32]	492	1			T222	2		T402	2		T399	17
values[33]	483	1			T222	2		T402	2		T399	14
values[34]	484	1			T222	2		T402	2		T399	10
values[35]	484	1			T222	2		T402	2		T399	9
values[36]	560	1			T222	2		T402	2		T399	21
values[37]	510	1			T222	2		T402	2		T399	9
values[38]	507	1			T222	2		T402	2		T399	6
values[39]	513	1			T222	2		T402	2		T399	7
values[40]	477	1			T222	2		T402	2		T399	10
values[41]	458	1			T222	2		T402	2		T399	20
values[42]	481	1			T222	2		T402	2		T399	25
values[43]	484	1			T222	2		T402	2		T399	8
values[44]	496	1			T222	2		T402	2		T399	7
values[45]	458	1			T222	2		T402	2		T399	10
values[46]	423	1			T222	2		T402	2		T399	7
values[47]	422	1			T222	2		T402	2		T399	10
values[48]	432	1			T222	2		T402	2		T399	10
values[49]	417	1			T222	2		T402	2		T399	13
values[50]	412	1			T222	2		T402	2		T399	9
values[51]	400	1			T222	2		T402	2		T399	11
values[52]	383	1			T222	2		T402	1		T399	10
values[53]	367	1			T222	2		T399	10		T503	1
values[54]	389	1			T222	2		T399	10		T503	2
values[55]	373	1			T222	2		T399	6		T503	2
values[56]	380	1			T222	2		T399	11		T503	1
values[57]	338	1			T222	2		T399	12		T503	2
values[58]	374	1			T222	2		T399	15		T503	2
values[59]	361	1			T222	2		T399	8		T503	1
values[60]	361	1			T222	2		T399	9		T503	3
values[61]	404	1			T222	2		T399	5		T503	3
values[62]	656	1			T222	2		T399	6		T503	4
values[63]	3075	1			T222	7		T399	2		T503	20
values[64]	25615	1			T222	114		T399	5		T503	51

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	651176	1			T69	1		T70	14		T71	5
values[2]	2711946	1			T69	126		T70	1351		T71	485
values[3]	1240292	1			T69	58		T70	453		T71	65
values[4]	149834	1			T70	16		T71	26		T74	15
values[5]	74246	1			T70	1		T71	19		T74	6
values[6]	47597	1			T71	25		T222	63		T388	49
values[7]	34836	1			T71	30		T222	48		T388	36
values[8]	27868	1			T71	21		T222	58		T388	38
values[9]	23791	1			T71	25		T222	38		T388	26
values[10]	21079	1			T71	24		T222	30		T388	49
values[11]	18978	1			T71	24		T222	36		T388	41
values[12]	17435	1			T71	15		T222	60		T388	40
values[13]	16004	1			T71	15		T222	16		T388	34
values[14]	15276	1			T71	12		T222	17		T388	32
values[15]	14385	1			T71	14		T222	11		T388	36
values[16]	13543	1			T71	13		T222	10		T388	37
values[17]	12996	1			T71	35		T222	16		T388	40
values[18]	12753	1			T71	38		T222	11		T388	54
values[19]	12304	1			T71	30		T222	14		T388	63
values[20]	11880	1			T71	37		T222	18		T388	47
values[21]	11178	1			T71	35		T222	20		T388	21
values[22]	10466	1			T71	16		T222	11		T388	19
values[23]	10077	1			T71	13		T222	11		T388	23
values[24]	9758	1			T71	10		T222	17		T388	14
values[25]	9453	1			T71	16		T222	6		T388	9
values[26]	9049	1			T71	27		T222	8		T388	14
values[27]	8662	1			T71	19		T222	6		T388	6
values[28]	8075	1			T71	17		T222	2		T388	15
values[29]	7599	1			T71	23		T388	24		T403	13
values[30]	6968	1			T71	7		T388	10		T403	15
values[31]	6572	1			T71	7		T388	32		T403	12
values[32]	6156	1			T71	3		T388	25		T403	10
values[33]	5463	1			T71	3		T388	23		T403	12
values[34]	5036	1			T71	3		T388	11		T403	14
values[35]	4830	1			T71	1		T388	6		T403	20
values[36]	4593	1			T71	1		T388	13		T403	32
values[37]	4385	1			T71	1		T388	5		T403	27
values[38]	4213	1			T71	3		T388	2		T403	23
values[39]	4089	1			T71	3		T403	21		T802	1
values[40]	3949	1			T71	1		T403	17		T802	1
values[41]	3879	1			T71	1		T403	16		T802	1
values[42]	3853	1			T71	2		T403	13		T802	1
values[43]	3609	1			T71	2		T403	10		T802	1
values[44]	3530	1			T71	3		T403	12		T802	1
values[45]	3473	1			T71	5		T403	16		T802	2
values[46]	3444	1			T71	1		T403	17		T802	1
values[47]	3319	1			T71	8		T403	15		T802	1
values[48]	3274	1			T71	4		T403	12		T802	1
values[49]	3320	1			T71	2		T403	13		T802	1
values[50]	3250	1			T71	3		T403	10		T802	1
values[51]	3204	1			T71	1		T403	21		T802	1
values[52]	3191	1			T71	3		T403	26		T802	1
values[53]	2972	1			T71	3		T403	22		T802	1
values[54]	2994	1			T403	27		T802	1		T817	2
values[55]	3004	1			T403	21		T802	1		T817	2
values[56]	2950	1			T403	28		T802	1		T817	2
values[57]	2769	1			T403	20		T802	1		T817	2
values[58]	2864	1			T403	20		T802	1		T817	2
values[59]	2736	1			T403	18		T802	1		T817	2
values[60]	2716	1			T403	16		T802	1		T817	2
values[61]	2825	1			T403	23		T802	1		T817	2
values[62]	4160	1			T403	53		T802	1		T817	2
values[63]	20031	1			T403	143		T802	1		T817	2
values[64]	225104	1			T403	240		T802	210		T817	361