Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2435768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27762991

1

T1

14153

T2

6928

T3

8356

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20111115	1			T1	5903		T2	2988		T3	4008
values[0x0]	8179741	1			T1	8250		T2	3940		T3	4348
values[0x1]	1907903	1			T1	592		T2	279		T3	483

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	640217	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29558542

1

T1

14745

T2

7207

T3

8839

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13973935	1			T1	7373		T2	3604		T3	4420
valid_sources[0x01]	13973580	1			T1	7372		T2	3603		T3	4419
valid_sources[0x02]	36623	1			T408	1		T42	2		T164	736
valid_sources[0x03]	36187	1			T62	1		T42	1		T164	928
valid_sources[0x04]	36148	1			T62	2		T72	1		T408	1
valid_sources[0x05]	36753	1			T408	1		T164	818		T512	13
valid_sources[0x06]	36524	1			T62	1		T408	1		T164	891
valid_sources[0x07]	36109	1			T62	1		T42	1		T164	707
valid_sources[0x08]	37683	1			T62	1		T42	1		T164	663
valid_sources[0x09]	36094	1			T62	2		T408	1		T42	1
valid_sources[0x0a]	36585	1			T408	1		T42	2		T164	883
valid_sources[0x0b]	35306	1			T62	1		T408	1		T164	760
valid_sources[0x0c]	35720	1			T408	1		T164	906		T512	82
valid_sources[0x0d]	36801	1			T20	6		T62	3		T408	1
valid_sources[0x0e]	35713	1			T164	798		T512	34		T165	848
valid_sources[0x0f]	35714	1			T62	1		T408	2		T164	743
valid_sources[0x10]	35927	1			T72	3		T164	803		T512	64
valid_sources[0x11]	37545	1			T62	1		T72	1		T42	1
valid_sources[0x12]	39518	1			T72	2		T408	1		T164	772
valid_sources[0x13]	35352	1			T20	4		T72	1		T164	717
valid_sources[0x14]	36439	1			T62	2		T408	1		T42	1
valid_sources[0x15]	36030	1			T408	1		T42	1		T164	706
valid_sources[0x16]	36757	1			T72	1		T42	1		T164	884
valid_sources[0x17]	34977	1			T72	1		T42	1		T164	699
valid_sources[0x18]	36188	1			T62	2		T72	1		T408	1
valid_sources[0x19]	37542	1			T20	12		T62	1		T408	1
valid_sources[0x1a]	35976	1			T62	2		T408	1		T164	811
valid_sources[0x1b]	35803	1			T72	2		T223	39		T164	940
valid_sources[0x1c]	35095	1			T408	1		T164	851		T512	63
valid_sources[0x1d]	36203	1			T72	1		T164	882		T512	26
valid_sources[0x1e]	36723	1			T72	2		T42	3		T164	888
valid_sources[0x1f]	35535	1			T408	1		T164	859		T512	49
valid_sources[0x20]	36969	1			T62	3		T42	2		T164	814

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19397126

1

T1

5903

T2

2988

T3

4008

values[0x0]

all_enables

biggest_size

8137387

1

T1

8250

T2

3940

T3

4348

values[0x1]

all_enables

biggest_size

228478

1

T20

23

T62

22

T72

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2872540	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

452755

1

T69

18

T70

274

T71

156

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1127817	1			T69	32		T70	641		T71	415
values[0x0]	1070531	1			T69	53		T70	672		T71	399
values[0x1]	1126947	1			T69	50		T70	634		T71	422

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2223524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1101771

1

T69

40

T70

645

T71

390

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52025	1			T69	3		T70	31		T71	8
valid_sources[0x01]	51806	1			T69	1		T70	44		T71	17
valid_sources[0x02]	51607	1			T69	1		T70	24		T71	6
valid_sources[0x03]	51905	1			T69	2		T70	29		T71	21
valid_sources[0x04]	51900	1			T69	1		T70	31		T71	20
valid_sources[0x05]	51527	1			T69	3		T70	26		T71	29
valid_sources[0x06]	52919	1			T69	4		T70	25		T71	16
valid_sources[0x07]	52549	1			T69	2		T70	34		T71	21
valid_sources[0x08]	51768	1			T70	33		T71	16		T73	40
valid_sources[0x09]	52518	1			T69	5		T70	30		T71	18
valid_sources[0x0a]	52677	1			T69	4		T70	36		T71	23
valid_sources[0x0b]	52042	1			T69	2		T70	32		T71	22
valid_sources[0x0c]	52119	1			T69	1		T70	14		T71	20
valid_sources[0x0d]	50778	1			T69	1		T70	32		T71	13
valid_sources[0x0e]	52094	1			T69	1		T70	41		T71	11
valid_sources[0x0f]	51432	1			T70	26		T71	16		T73	37
valid_sources[0x10]	51977	1			T69	1		T70	25		T71	31
valid_sources[0x11]	52457	1			T69	1		T70	31		T71	19
valid_sources[0x12]	52737	1			T69	3		T70	29		T71	25
valid_sources[0x13]	52353	1			T70	16		T71	9		T73	40
valid_sources[0x14]	52237	1			T69	3		T70	57		T71	30
valid_sources[0x15]	51927	1			T69	2		T70	60		T71	8
valid_sources[0x16]	52351	1			T70	34		T71	16		T73	43
valid_sources[0x17]	52144	1			T69	1		T70	36		T71	12
valid_sources[0x18]	51435	1			T69	2		T70	15		T71	19
valid_sources[0x19]	52468	1			T69	3		T70	35		T71	15
valid_sources[0x1a]	50808	1			T70	40		T71	18		T73	34
valid_sources[0x1b]	50855	1			T69	4		T70	25		T71	23
valid_sources[0x1c]	52883	1			T69	3		T70	32		T71	36
valid_sources[0x1d]	51478	1			T69	2		T70	35		T71	33
valid_sources[0x1e]	52458	1			T69	1		T70	40		T71	25
valid_sources[0x1f]	50814	1			T69	1		T70	51		T71	23
valid_sources[0x20]	51284	1			T69	3		T70	27		T71	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47907

1

T69

2

T70

26

T71

14

values[0x0]

all_enables

biggest_size

356889

1

T69

15

T70

217

T71

122

values[0x1]

all_enables

biggest_size

47959

1

T69

1

T70

31

T71

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3049452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

495704

1

T69

19

T70

306

T71

153

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1215372	1			T69	61		T70	725		T71	413
values[0x0]	1115001	1			T69	50		T70	701		T71	359
values[0x1]	1214783	1			T69	49		T70	689		T71	396

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2339331	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1205825

1

T69

48

T70

716

T71

379

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55077	1			T70	21		T71	3		T73	48
valid_sources[0x01]	55626	1			T70	22		T71	1		T73	42
valid_sources[0x02]	55917	1			T70	68		T71	4		T73	25
valid_sources[0x03]	55057	1			T69	6		T70	44		T71	38
valid_sources[0x04]	55695	1			T70	19		T71	8		T73	59
valid_sources[0x05]	55087	1			T70	17		T71	18		T73	40
valid_sources[0x06]	56135	1			T69	1		T70	49		T71	12
valid_sources[0x07]	54835	1			T69	2		T70	45		T71	3
valid_sources[0x08]	55451	1			T69	4		T70	26		T71	35
valid_sources[0x09]	55773	1			T70	25		T71	3		T73	43
valid_sources[0x0a]	54863	1			T70	31		T71	10		T73	54
valid_sources[0x0b]	55814	1			T70	38		T71	5		T73	25
valid_sources[0x0c]	54669	1			T70	25		T71	31		T73	46
valid_sources[0x0d]	54361	1			T70	47		T71	7		T73	65
valid_sources[0x0e]	54919	1			T70	26		T71	1		T73	38
valid_sources[0x0f]	55238	1			T69	3		T70	34		T71	22
valid_sources[0x10]	56272	1			T70	8		T71	9		T73	46
valid_sources[0x11]	56124	1			T70	50		T71	20		T73	38
valid_sources[0x12]	55174	1			T69	12		T70	38		T71	10
valid_sources[0x13]	55841	1			T70	43		T71	19		T73	72
valid_sources[0x14]	55054	1			T70	69		T71	18		T73	58
valid_sources[0x15]	55647	1			T70	40		T71	14		T73	45
valid_sources[0x16]	56242	1			T69	5		T70	36		T71	12
valid_sources[0x17]	54903	1			T69	4		T70	33		T71	1
valid_sources[0x18]	55333	1			T69	19		T70	26		T71	27
valid_sources[0x19]	55637	1			T69	2		T70	12		T71	42
valid_sources[0x1a]	54427	1			T69	2		T70	33		T71	32
valid_sources[0x1b]	56985	1			T69	5		T70	31		T71	34
valid_sources[0x1c]	55951	1			T69	4		T70	23		T71	28
valid_sources[0x1d]	55124	1			T70	51		T73	47		T74	6
valid_sources[0x1e]	55953	1			T70	50		T71	26		T73	40
valid_sources[0x1f]	55976	1			T70	40		T71	30		T73	42
valid_sources[0x20]	55340	1			T69	11		T70	19		T71	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52593

1

T69

4

T70

34

T71

18

values[0x0]

all_enables

biggest_size

390966

1

T69

13

T70

240

T71

125

values[0x1]

all_enables

biggest_size

52145

1

T69

2

T70

32

T71

10

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2900139	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

458528

1

T69

24

T70

235

T71

158

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1138747	1			T69	67		T70	574		T71	394
values[0x0]	1082236	1			T69	67		T70	602		T71	405
values[0x1]	1137684	1			T69	51		T70	659		T71	406

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2245215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1113452

1

T69

57

T70

588

T71

397

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52064	1			T69	1		T70	18		T71	8
valid_sources[0x01]	52820	1			T69	2		T70	22		T71	17
valid_sources[0x02]	52335	1			T69	4		T70	22		T71	27
valid_sources[0x03]	53038	1			T69	1		T70	17		T71	9
valid_sources[0x04]	52793	1			T69	5		T70	17		T71	26
valid_sources[0x05]	52546	1			T70	35		T71	21		T73	33
valid_sources[0x06]	52254	1			T69	5		T70	20		T71	19
valid_sources[0x07]	52253	1			T69	7		T70	31		T71	16
valid_sources[0x08]	53000	1			T69	3		T70	36		T71	16
valid_sources[0x09]	52255	1			T69	4		T70	26		T71	24
valid_sources[0x0a]	51307	1			T69	2		T70	27		T71	22
valid_sources[0x0b]	53166	1			T69	3		T70	35		T71	14
valid_sources[0x0c]	51745	1			T69	3		T70	24		T71	43
valid_sources[0x0d]	52336	1			T69	4		T70	24		T71	9
valid_sources[0x0e]	53296	1			T69	4		T70	24		T71	14
valid_sources[0x0f]	52566	1			T69	6		T70	28		T71	31
valid_sources[0x10]	53480	1			T69	2		T70	19		T71	18
valid_sources[0x11]	52644	1			T69	2		T70	28		T71	29
valid_sources[0x12]	52816	1			T69	8		T70	27		T71	20
valid_sources[0x13]	52106	1			T69	2		T70	34		T71	10
valid_sources[0x14]	52079	1			T69	2		T70	36		T71	15
valid_sources[0x15]	52004	1			T69	2		T70	41		T71	22
valid_sources[0x16]	52142	1			T69	1		T70	16		T71	27
valid_sources[0x17]	51572	1			T69	2		T70	30		T71	15
valid_sources[0x18]	52185	1			T69	2		T70	41		T71	19
valid_sources[0x19]	53116	1			T69	11		T70	33		T71	5
valid_sources[0x1a]	52817	1			T69	3		T70	33		T71	23
valid_sources[0x1b]	51953	1			T70	23		T71	20		T73	34
valid_sources[0x1c]	52454	1			T69	2		T70	42		T71	16
valid_sources[0x1d]	52599	1			T69	2		T70	18		T71	19
valid_sources[0x1e]	52695	1			T70	28		T71	42		T73	37
valid_sources[0x1f]	51894	1			T69	6		T70	37		T71	10
valid_sources[0x20]	52050	1			T69	3		T70	30		T71	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48296

1

T69

2

T70

19

T71

19

values[0x0]

all_enables

biggest_size

361832

1

T69

20

T70

189

T71

121

values[0x1]

all_enables

biggest_size

48400

1

T69

2

T70

27

T71

18