Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T70,T74,T222	Yes	T69,T70,T71	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T73,T74,T222	Yes	T73,T74,T222	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T190,T102,T191	Yes	T190,T102,T191	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T20,T62,T72	Yes	T20,T62,T72	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T20,T42,T223	Yes	T20,T42,T223	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T20,T42,T223	Yes	T20,T42,T223	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T55,T56,T193	Yes	T55,T56,T193	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T20,T61,T62	Yes	T20,T61,T62	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T20,T61,T62	Yes	T20,T61,T62	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T20,T61,T62	Yes	T20,T61,T62	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T20,T61,T62	Yes	T20,T61,T62	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T20,T61,T62	Yes	T20,T61,T62	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T20,T62,T107	Yes	T20,T62,T107	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T20,*T61,*T62	Yes	T20,T61,T62	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T20,T61,T62	Yes	T20,T61,T62	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T69,T70	Yes	T42,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T42,T69,T70	Yes	T42,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T42,T69,T70	Yes	T42,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T42,T69,T70	Yes	T42,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T42,T69,T70	Yes	T42,T69,T70	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T42,T69,T70	Yes	T42,T69,T70	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T42,T70,T74	Yes	T42,T69,T70	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T73	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T69,T70	Yes	T42,T69,T70	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T42,T69,T70	Yes	T42,T69,T70	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T42,T70,T73	Yes	T42,T69,T70	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T71	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T42,*T69,*T70	Yes	T42,T69,T70	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T42,T69,T70	Yes	T42,T69,T70	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T20,T42,T182	Yes	T20,T42,T182	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T20,T42,T182	Yes	T20,T42,T182	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T20,T42,T182	Yes	T20,T42,T182	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T20,T42,T182	Yes	T20,T42,T182	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T20,T42,T182	Yes	T20,T42,T182	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T182,*T183,*T227	Yes	T182,T183,T227	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T20,T42,T182	Yes	T20,T42,T182	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T32	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T182,T183,T227	Yes	T182,T183,T227	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T42,T182	Yes	T20,T42,T182	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T32	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T182,*T183,*T227	Yes	T182,T183,T227	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T4,T32	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T20,T42,T182	Yes	T20,T42,T182	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T4,T405,T63	Yes	T4,T405,T63	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T72,T406,T89	Yes	T72,T406,T89	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T50,T51,T42	Yes	T50,T51,T42	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T274,T50,T351	Yes	T274,T50,T351	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T274,T50,T351	Yes	T274,T50,T351	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T50,T51,T42	Yes	T50,T51,T42	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T274,T50,T351	Yes	T274,T50,T351	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T42,*T69,T70	Yes	T42,T69,T70	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T274,T50,T351	Yes	T274,T50,T351	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T274,T50,T351	Yes	T274,T50,T351	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T274,T351,T352	Yes	T274,T351,T352	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T69,T70	Yes	T50,T51,T42	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T274,T351,T352	Yes	T274,T50,T351	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T42,T70,T73	Yes	T42,T69,T70	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T352,*T42,*T407	Yes	T274,T351,T352	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T274,T50,T351	Yes	T274,T50,T351	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T20,*T61,*T62	Yes	T20,T61,T62	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T20,T62,T72	Yes	T20,T62,T72	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T315,T115,T250	Yes	T315,T115,T250	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T20,*T61,*T62	Yes	T20,T61,T62	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T55,T10,T11	Yes	T55,T10,T11	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T55,T10,T11	Yes	T55,T10,T11	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T10,T11	Yes	T55,T10,T11	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T55,T10,T11	Yes	T55,T10,T11	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T55,T10,T11	Yes	T55,T10,T11	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T55,T10,T11	Yes	T55,T10,T11	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T20,*T69,*T70	Yes	T20,T69,T70	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T11,T169,T189	Yes	T11,T169,T189	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T55,T10,T11	Yes	T55,T10,T11	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T55,T10,T11	Yes	T55,T10,T11	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T70,T73,T74	Yes	T69,T70,T73	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T20	Yes	T10,T11,T20	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T55,T10,T11	Yes	T55,T10,T11	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T11,T20	Yes	T10,T11,T20	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T20,*T70,*T73	Yes	T20,T69,T70	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T11,*T20	Yes	T10,T11,T20	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T55,T10,T11	Yes	T55,T10,T11	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T20,T109,T356	Yes	T20,T109,T356	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T20,T109,T33	Yes	T20,T109,T33	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T20,T109,T356	Yes	T20,T109,T356	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T20,T109,T356	Yes	T20,T109,T356	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T20,T109,T33	Yes	T20,T109,T33	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T20,T109,T356	Yes	T20,T109,T356	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T20,*T69,*T70	Yes	T20,T69,T70	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T20,T109,T356	Yes	T20,T109,T356	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T20,T109,T356	Yes	T20,T109,T356	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T20,T109,T33	Yes	T20,T109,T33	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T109,T356	Yes	T20,T109,T356	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T20,T109,T33	Yes	T20,T109,T33	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T70,T73,T74	Yes	T69,T70,T73	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T20,*T70,*T73	Yes	T20,T69,T70	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T20,*T109,*T356	Yes	T20,T109,T356	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T20,T109,T356	Yes	T20,T109,T356	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T126,T16,T17	Yes	T126,T16,T17	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T126,T16,T17	Yes	T126,T16,T17	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T126,T16,T17	Yes	T126,T16,T17	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T126,T16,T17	Yes	T126,T16,T17	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T16,T17,T355	Yes	T16,T17,T355	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T126,T16,T17	Yes	T126,T16,T17	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T73	Yes	T69,T70,T73	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T126,T16,T17	Yes	T126,T16,T17	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T126,T16,T17	Yes	T126,T16,T17	INPUT
tl_usbdev_i.d_error	Yes	Yes	T69,T70,T73	Yes	T69,T70,T71	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T126,T356,T355	Yes	T126,T356,T355	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T126,T356,T355	Yes	T126,T356,T355	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T126,T16,T17	Yes	T126,T16,T17	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T71	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T73	Yes	T69,T70,T73	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T126,*T16,*T17	Yes	T126,T16,T17	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T126,T16,T17	Yes	T126,T16,T17	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T62,*T69,*T70	Yes	T62,T69,T70	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T32	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T32	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T62,*T69,*T70	Yes	T62,T69,T70	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T62,T69,T70	Yes	T62,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T62,T69,T70	Yes	T62,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T62,T69,T70	Yes	T62,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T62,T69,T70	Yes	T62,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T62,T69,T70	Yes	T62,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T62,T69,T70	Yes	T62,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T62,T69,T70	Yes	T62,T69,T70	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T62,T70,T74	Yes	T62,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T62,T69,T70	Yes	T62,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T62,T69,T70	Yes	T62,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T62,T69,T70	Yes	T62,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T62,T69,T70	Yes	T62,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T62,*T69,*T70	Yes	T62,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T62,T69,T70	Yes	T62,T69,T70	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T32	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T62,*T69,*T70	Yes	T62,T69,T70	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T269,T236,T245	Yes	T269,T236,T245	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	INPUT
tl_hmac_i.d_error	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	INPUT
tl_hmac_i.d_sink	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T62,*T70,*T73	Yes	T62,T70,T73	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T4,*T269,*T38	Yes	T4,T269,T38	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T4,T269,T38	Yes	T4,T269,T38	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T62,*T42,*T69	Yes	T62,T42,T69	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T412,T128,T413	Yes	T412,T128,T413	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	INPUT
tl_kmac_i.d_error	Yes	Yes	T69,T70,T71	Yes	T70,T73,T74	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	INPUT
tl_kmac_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T62,*T42,*T70	Yes	T62,T42,T69	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T412,*T128,*T62	Yes	T412,T128,T62	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T412,T128,T62	Yes	T412,T128,T62	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T20,*T69,*T70	Yes	T20,T69,T70	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	INPUT
tl_aes_i.d_error	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	INPUT
tl_aes_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T70,T73,T74	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T20,*T70,*T73	Yes	T20,T69,T70	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T677,*T148,*T20	Yes	T677,T148,T20	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T677,T148,T20	Yes	T677,T148,T20	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T62,*T69,*T70	Yes	T62,T69,T70	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T80,T49	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T80,T4	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T62,*T70,*T73	Yes	T62,T69,T70	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T70,T73,T74	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T80,*T49,*T147	Yes	T80,T49,T147	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T20,*T62,*T69	Yes	T20,T62,T69	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T70,T73,T74	Yes	T69,T70,T73	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T80,T49	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T20,*T62,*T70	Yes	T20,T62,T70	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T73	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T80,*T49,*T147	Yes	T80,T49,T147	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T62,*T69,*T70	Yes	T62,T69,T70	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T80,T49	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T80,T49	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T62,*T70,*T73	Yes	T62,T69,T70	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T80,*T49,*T147	Yes	T80,T49,T147	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T80,T49	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T62,*T69,*T70	Yes	T62,T69,T70	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	INPUT
tl_edn1_i.d_error	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T147,T148	Yes	T80,T49,T147	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T49,T147,T148	Yes	T80,T49,T147	INPUT
tl_edn1_i.d_sink	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T62,*T70,*T73	Yes	T62,T69,T70	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T80,*T49,*T147	Yes	T80,T49,T147	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T80,T49,T147	Yes	T80,T49,T147	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T49,T269,T54	Yes	T49,T269,T54	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T49	Yes	T2,T3,T49	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T49	Yes	T2,T3,T49	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T2,T3,T49	Yes	T2,T3,T49	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T2,T3,T49	Yes	T2,T3,T49	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T20,*T69,*T70	Yes	T20,T69,T70	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T2,T3,T49	Yes	T2,T3,T49	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T2,T3,T49	Yes	T2,T3,T49	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T69,T70,T73	Yes	T70,T73,T74	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T49,T269,T54	Yes	T49,T269,T54	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T49	Yes	T2,T3,T49	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T2,T3,T49	Yes	T2,T3,T49	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T70,T73,T74	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T20,*T70,*T73	Yes	T20,T69,T70	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T49	Yes	T2,T3,T49	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T2,T3,T49	Yes	T2,T3,T49	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T49,T4	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T72,*T408,*T42	Yes	T72,T408,T42	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	INPUT
tl_otbn_i.d_error	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	INPUT
tl_otbn_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T72,*T408,*T42	Yes	T72,T408,T42	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T49,*T4,*T38	Yes	T49,T4,T38	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T49,T4,T38	Yes	T49,T4,T38	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T32,T128,T62	Yes	T32,T128,T62	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T32,T128,T62	Yes	T32,T128,T62	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T32,T128,T62	Yes	T32,T128,T62	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T128,T62,T109	Yes	T128,T62,T109	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T32,T128,T62	Yes	T32,T128,T62	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T62,*T69,*T70	Yes	T62,T69,T70	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T32,T128,T62	Yes	T32,T128,T62	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T32,T128,T62	Yes	T32,T128,T62	INPUT
tl_keymgr_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T128,T62,T109	Yes	T128,T62,T109	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T128,T62	Yes	T32,T128,T62	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T32,T128,T62	Yes	T32,T128,T62	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T62,*T70,*T71	Yes	T62,T69,T70	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T128,*T62,*T109	Yes	T32,T128,T62	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T32,T128,T62	Yes	T32,T128,T62	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T42,*T69,*T70	Yes	T42,T69,T70	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T42,T69,T70	Yes	T42,T69,T70	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T70,T73,T74	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T42,*T70,*T73	Yes	T42,T69,T70	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T4,T32	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T129	Yes	T1,T4,T129	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T129	Yes	T1,T4,T129	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T129	Yes	T1,T4,T129	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T1,T4,T129	Yes	T1,T4,T129	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T1,T4,T129	Yes	T1,T4,T129	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T20,*T69,*T70	Yes	T20,T69,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T1,T4,T129	Yes	T1,T4,T129	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T1,T4,T129	Yes	T1,T4,T129	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T20,T69,T70	Yes	T20,T69,T70	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T4,T129	Yes	T1,T4,T129	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T1,T4,T129	Yes	T1,T4,T129	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T70,T71,T73	Yes	T69,T70,T71	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T20,*T70,*T71	Yes	T20,T69,T70	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T1,*T129,*T20	Yes	T1,T129,T20	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T1,T4,T129	Yes	T1,T4,T129	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T32	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range