Unified Coverage Report :: Module Instance :: tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T20,T62
0	1	Covered	T13,T168,T15
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T168,T15
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T168,T15

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T168,T15
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T168,T15

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T168,T15

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T168,T15
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T20,T62
0	1	Covered	T13,T15,T26
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T15,T26
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T15,T26
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T26
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T171,T20
0	1	Covered	T13,T171,T35
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T15,T26
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T171,T15

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T171,T15
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T171,T15

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T171,T15

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T36,T37

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T171,T15
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T37
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T171,T20
0	1	Covered	T13,T171,T15
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T15,T26
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T171,T15

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T171,T15
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T171,T15

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T171,T15

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T171,T15
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T20,T62,T72
0	1	Covered	T12,T33,T7
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T10,T11,T169
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T33,T7,T34

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T33,T7,T34
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T7,T34

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T33,T7,T34

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T33,T34

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T33,T7,T34
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T12,T33,T34
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T20,T62,T72
0	1	Covered	T10,T11,T12
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T12,T33,T7
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T33,T7,T34

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T33,T7,T34
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T7,T34

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T33,T7,T34

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T33,T7,T34
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T20,T62,T72
0	1	Covered	T8,T9,T29
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T8,T9,T29
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T9

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T8,T9
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T9

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T20,T62,T21
0	1	Covered	T10,T11,T12
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T33,T34,T9
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T33,T7,T34

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T33,T7,T34
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T7,T34

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T33,T7,T34

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T33,T7,T34
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T145,T173,T174
0	1	Covered	T145,T173,T174
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T29,T30
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T29

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T8,T29
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T29

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T29

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T33,T34

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T29
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T12,T33,T34
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T145,T173,T174
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T2,T3

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T2,T3

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T33,T34

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T12,T33,T34
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T20,T62
0	1	Covered	T13,T12,T21
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T15,T26
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T15,T26
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T33,T34

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T26
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T12,T33,T34
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T116,T13,T20
0	1	Covered	T116,T13,T16
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T116,T13,T21
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T116,T13,T21

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T116,T13,T21
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T116,T13,T21

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T116,T13,T21

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T116,T13,T21
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T20,T62
0	1	Covered	T13,T15,T170
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T15,T26
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T15,T26

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T15,T26
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T15,T26

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T15,T26

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T26
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T20,T62
0	1	Covered	T13,T175,T21
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T21,T15
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T175,T21

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T175,T21
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T175,T21

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T175,T21

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T175,T21
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T117,T137
0	1	Covered	T13,T117,T137
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T117,T137
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T117,T137

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T117,T137
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T117,T137

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T117,T137

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T117,T137
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T117,T137
0	1	Covered	T13,T117,T137
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T117,T137
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T117,T137

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T117,T137
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T117,T137

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T117,T137

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T117,T137
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T117,T137
0	1	Covered	T13,T117,T137
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T117,T137
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T117,T137

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T117,T137
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T117,T137

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T117,T137

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T117,T137
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T38,T39
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T9,T29

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T9,T29
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T9,T29

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T9,T29

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T38,T39

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T29
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T38,T39
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T61,T177,T178
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T8,T29
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T9

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T8,T9
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T9

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T38,T39

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T38,T39
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T61,T177,T178
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T8,T29
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T29

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T8,T29
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T29

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T29

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T38,T39

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T29
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T38,T39
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T20,T62,T179
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T8,T9,T29
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T9

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T8,T9
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T9

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T38,T39
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T2,T3

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T2,T3

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T32,T63,T66
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T29,T30
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T29

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T7,T8,T29
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T29

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T7,T8,T29

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T29
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T53,T5,T6
0	1	Covered	T53,T5,T6
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T9,T29,T30
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T8,T9,T29

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T8,T9,T29
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T29

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T8,T9,T29

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T29
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T116,T20,T62
0	1	Covered	T21,T170,T172
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T21,T354,T691
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T21,T354,T691

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T21,T354,T691
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T354,T691

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T21,T354,T691

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T21,T354,T691
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T53,T5,T6
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T8,T9,T29

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T8,T9,T29
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T29

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T8,T9,T29

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T29
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T116,T13,T20
0	1	Covered	T116,T13,T21
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T21,T15
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T21,T15

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T21,T15
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T21,T15

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T21,T15

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T21,T15
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T117,T137
0	1	Covered	T13,T117,T137
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T117,T137
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T117,T137

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T117,T137
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T117,T137

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T117,T137

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T117,T137
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	91	1	1	100.00

Line No.	Covered	Statements
39		unreachable
74	1	1
76	1	1
80	1	1
81	1	1
88	1	1
89	1	1
91	1	1

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION (ie_i ? inout_io : 1'bz)
             --1-

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T13,T117,T137
0	1	Covered	T13,T117,T137
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       80
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T117,T137
1	1	Covered	T29,T30,T31

 LINE       81
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T117,T137

 LINE       81
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31

 LINE       81
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T29,T30,T31

 LINE       88
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       88
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T13,T117,T137
1	1	Covered	T29,T30,T31

 LINE       89
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T117,T137

 LINE       89
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T30,T31
1	1	Covered	T13,T117,T137

 LINE       91
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	74	1	1	100.00
TERNARY	88	2	2	100.00
TERNARY	89	2	2	100.00
TERNARY	91	2	2	100.00



	LineNo.	Expression
-1-:	74	(ie_i) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable



	LineNo.	Expression
-1-:	88	((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	89	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T117,T137
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	91	(attr_i.pull_en) ?

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	955	955	0	0

AnalogNoScan_A

Name	Attempts	Real Successes
Total	955	955
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T32	1	1
T49	1	1
T53	1	1
T79	1	1
T80	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[5].u_mio_pad

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[6].u_mio_pad

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[7].u_mio_pad