| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 41.15 | 52.12 | 46.44 | 24.45 | 59.86 | 54.58 | 9.43 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 40.44 | 40.44 | 51.84 | 51.84 | 46.30 | 46.30 | 20.13 | 20.13 | 59.86 | 59.86 | 55.08 | 55.08 | 9.43 | 9.43 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.121254610 | ||
| 40.83 | 0.39 | 51.84 | 0.00 | 46.36 | 0.06 | 22.41 | 2.28 | 59.86 | 0.00 | 55.08 | 0.00 | 9.43 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4101732627 | ||
| 41.02 | 0.19 | 51.84 | 0.00 | 46.38 | 0.03 | 23.51 | 1.10 | 59.86 | 0.00 | 55.08 | 0.00 | 9.43 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2648162737 | ||
| 41.10 | 0.09 | 51.84 | 0.00 | 46.42 | 0.04 | 23.99 | 0.48 | 59.86 | 0.00 | 55.08 | 0.00 | 9.43 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2356016935 | ||
| 41.15 | 0.04 | 51.84 | 0.00 | 46.42 | 0.01 | 24.26 | 0.26 | 59.86 | 0.00 | 55.08 | 0.00 | 9.43 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.18335880 | ||
| 41.17 | 0.02 | 51.84 | 0.00 | 46.44 | 0.02 | 24.37 | 0.11 | 59.86 | 0.00 | 55.08 | 0.00 | 9.43 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2722343016 | ||
| 41.18 | 0.01 | 51.84 | 0.00 | 46.44 | 0.00 | 24.43 | 0.06 | 59.86 | 0.00 | 55.08 | 0.00 | 9.43 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3226048417 | ||
| 41.18 | 0.01 | 51.84 | 0.00 | 46.44 | 0.00 | 24.44 | 0.01 | 59.86 | 0.00 | 55.08 | 0.00 | 9.43 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3412866696 | ||
| 41.18 | 0.01 | 51.84 | 0.00 | 46.44 | 0.00 | 24.45 | 0.01 | 59.86 | 0.00 | 55.08 | 0.00 | 9.43 | 0.00 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2204282109 | ||
| Name |
|---|
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1843270101 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3226048417 | Mar 14 02:13:28 PM PDT 24 | Mar 14 02:18:50 PM PDT 24 | 5458165108 ps | ||
| T2 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3412866696 | Mar 14 02:13:27 PM PDT 24 | Mar 14 02:16:41 PM PDT 24 | 4260439368 ps | ||
| T3 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.121254610 | Mar 14 02:13:28 PM PDT 24 | Mar 14 02:19:16 PM PDT 24 | 5469256910 ps | ||
| T4 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.18335880 | Mar 14 02:13:28 PM PDT 24 | Mar 14 02:17:00 PM PDT 24 | 4161847685 ps | ||
| T5 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2722343016 | Mar 14 02:13:28 PM PDT 24 | Mar 14 02:17:12 PM PDT 24 | 3978107960 ps | ||
| T6 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2648162737 | Mar 14 02:13:38 PM PDT 24 | Mar 14 02:19:37 PM PDT 24 | 6131400089 ps | ||
| T7 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1843270101 | Mar 14 02:13:44 PM PDT 24 | Mar 14 02:16:56 PM PDT 24 | 4834534932 ps | ||
| T8 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2356016935 | Mar 14 02:13:33 PM PDT 24 | Mar 14 02:17:12 PM PDT 24 | 4273809644 ps | ||
| T9 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4101732627 | Mar 14 02:13:29 PM PDT 24 | Mar 14 02:17:24 PM PDT 24 | 5481146236 ps | ||
| T10 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2204282109 | Mar 14 02:13:45 PM PDT 24 | Mar 14 02:17:14 PM PDT 24 | 4975084659 ps |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.121254610 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5469256910 ps |
| CPU time | 348.22 seconds |
| Started | Mar 14 02:13:28 PM PDT 24 |
| Finished | Mar 14 02:19:16 PM PDT 24 |
| Peak memory | 638060 kb |
| Host | smart-070d7cda-bd23-4c54-bf69-4de162a73850 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121254610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 0.chip_padctrl_attributes.121254610 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.4101732627 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5481146236 ps |
| CPU time | 235.05 seconds |
| Started | Mar 14 02:13:29 PM PDT 24 |
| Finished | Mar 14 02:17:24 PM PDT 24 |
| Peak memory | 635992 kb |
| Host | smart-719c0401-5124-48f3-a405-d4142aa821f4 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101732627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.4101732627 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2648162737 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6131400089 ps |
| CPU time | 358.74 seconds |
| Started | Mar 14 02:13:38 PM PDT 24 |
| Finished | Mar 14 02:19:37 PM PDT 24 |
| Peak memory | 638168 kb |
| Host | smart-a0f686b0-0e1f-498a-845a-ccd1f6efaf3b |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648162737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.2648162737 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2356016935 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4273809644 ps |
| CPU time | 219.04 seconds |
| Started | Mar 14 02:13:33 PM PDT 24 |
| Finished | Mar 14 02:17:12 PM PDT 24 |
| Peak memory | 638184 kb |
| Host | smart-1be7a48d-56f6-4e0a-9dda-e2fb923aef6c |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356016935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.2356016935 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.18335880 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4161847685 ps |
| CPU time | 211.49 seconds |
| Started | Mar 14 02:13:28 PM PDT 24 |
| Finished | Mar 14 02:17:00 PM PDT 24 |
| Peak memory | 634948 kb |
| Host | smart-b873592a-901d-49c3-84ca-49c187bc06ee |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18335880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 4.chip_padctrl_attributes.18335880 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2722343016 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3978107960 ps |
| CPU time | 223.59 seconds |
| Started | Mar 14 02:13:28 PM PDT 24 |
| Finished | Mar 14 02:17:12 PM PDT 24 |
| Peak memory | 638024 kb |
| Host | smart-c1bea50a-15f1-4eae-b6c4-a80ea3bdb0e4 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722343016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.2722343016 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3226048417 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5458165108 ps |
| CPU time | 322.25 seconds |
| Started | Mar 14 02:13:28 PM PDT 24 |
| Finished | Mar 14 02:18:50 PM PDT 24 |
| Peak memory | 638100 kb |
| Host | smart-f2fbc715-77c5-4c77-870a-34d9e832e2b4 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226048417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.3226048417 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3412866696 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4260439368 ps |
| CPU time | 194.06 seconds |
| Started | Mar 14 02:13:27 PM PDT 24 |
| Finished | Mar 14 02:16:41 PM PDT 24 |
| Peak memory | 638168 kb |
| Host | smart-bcd85ea8-8900-457c-b3c2-8a0ca015d870 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412866696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.3412866696 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2204282109 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4975084659 ps |
| CPU time | 209.22 seconds |
| Started | Mar 14 02:13:45 PM PDT 24 |
| Finished | Mar 14 02:17:14 PM PDT 24 |
| Peak memory | 638200 kb |
| Host | smart-97ad87fd-ff29-42a2-b912-c3655f5bdb79 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204282109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2204282109 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1843270101 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4834534932 ps |
| CPU time | 191.86 seconds |
| Started | Mar 14 02:13:44 PM PDT 24 |
| Finished | Mar 14 02:16:56 PM PDT 24 |
| Peak memory | 638196 kb |
| Host | smart-6e9189a4-a1b1-4f43-b3b8-5b1d3e24a1c1 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843270101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.1843270101 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
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