Design Module List
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Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
42.85 53.83 36.77 23.92 44.40 55.35


Total modules in report: 108
modlist.html | modlist1.html
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
prim_lc_sender 0.00 0.00
pinmux_jtag_breakout 0.00 0.00 0.00
prim_mubi4_dec 0.00 0.00
prim_sync_reqack_data 0.00 0.00 0.00
prim_generic_clock_buf 0.00 0.00
rv_plic_reg_top 0.52 0.26 0.35 1.47 0.00
entropy_src 1.08 1.08
otbn 1.31 1.31
aes 1.55 1.55
csrng 1.68 1.68
edn 1.99 1.99
ibex_top 2.43 2.43
rv_dm 3.21 3.21
prim_arbiter_fixed 3.45 0.00 6.67 0.00 7.14
flash_ctrl 3.55 3.55
rv_core_ibex_cfg_reg_top 4.37 2.81 6.11 8.57 0.00
hmac 5.70 5.70
usbdev 5.97 5.97
xbar_main 5.98 5.98
spi_host 10.06 10.06
keymgr 11.72 11.72
sram_ctrl 13.30 13.30
rv_plic 16.28 0.00 0.00 1.41 0.00 80.00
prim_reg_cdc_arb 19.44 17.00 25.97 34.78 0.00
prim_reg_cdc_arb 17.39 34.78 0.00
prim_reg_cdc_arb ( parameter DataWidth=10,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=9,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 + DataWidth=8,ResetVal=0,DstWrReq=1 + DataWidth=32,ResetVal=0,DstWrReq=1 ) 26.30 34.00 18.60
prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 + DataWidth=6,ResetVal=0,DstWrReq=0 + DataWidth=13,ResetVal=0,DstWrReq=0 ) 16.67 0.00 33.33
uart 21.57 21.57
i2c 21.95 21.95
adc_ctrl 22.22 22.22
pattgen 22.67 22.67
rv_timer 23.29 23.29
pwm 23.53 23.53
aon_timer 23.57 23.57
gpio 23.70 23.70
xbar_peri 23.91 23.91
kmac 25.36 25.36
pinmux_wkup 25.56 26.32 23.08 27.27
otp_ctrl 25.62 25.62
spi_device 26.42 26.42
prim_esc_receiver 28.57 28.57
alert_handler 28.60 28.60
sysrst_ctrl 29.34 29.34
rv_core_ibex 31.90 28.24 14.29 17.73 58.33 40.91
tlul_adapter_host 32.98 44.07 30.09 57.78 0.00
tlul_adapter_host 0.00 0.00
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 ) 50.09 60.87 29.41 60.00
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 ) 37.87 27.27 30.77 55.56
prim_alert_sender 33.33 33.33
prim_edn_req 35.19 50.00 30.77 60.00 0.00
sensor_ctrl 35.80 7.14 3.00 18.86 100.00 50.00
lc_ctrl 36.27 36.27
rv_core_addr_trans 36.58 1.41 58.33 50.00
pwrmgr 37.61 37.61
prim_sync_reqack 38.19 69.44 33.33 50.00 0.00
pinmux_reg_top 40.97 85.95 42.92 35.00 0.00
prim_max_tree 41.04 0.00 39.00 58.49 66.67
rstmgr 41.23 41.23
prim_reg_cdc 43.78 45.45 29.67 50.00 50.00
prim_reg_cdc 48.48 45.45 50.00 50.00
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 ) 30.77 30.77
prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=10,ResetVal=0,BitMask=769,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal=9,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 ) 28.57 28.57
tlul_socket_1n 44.87 16.07 31.82 31.58 100.00
ast 47.29 47.29
prim_lc_or_hardened 47.62 0.00 42.86 100.00
sensor_ctrl_reg_top 49.45 54.63 50.57 92.59 0.00
padring 49.72 49.72
tlul_err_resp 49.87 57.69 36.36 55.56
prim_generic_usb_diff_rx 50.00 66.67 33.33 50.00
clkmgr 50.98 50.98
rv_plic_gateway 52.27 81.82 0.00 75.00
prim_pulse_sync 52.68 85.71 25.00 100.00 0.00
prim_packer_fifo 53.31 81.82 60.00 71.43 0.00
rv_plic_target 57.41 55.56 50.00 66.67
pinmux 59.41 70.71 48.46 59.86 34.02 84.00
top_earlgrey 66.26 51.61 47.17 100.00
prim_lc_sync 66.67 33.33 100.00
prim_lc_sync 100.00 100.00
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) 100.00 100.00
prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 ) 33.33 33.33
prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 0.00 0.00
prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 ) 0.00 0.00
pinmux_strap_sampling 67.66 92.41 50.91 50.85 76.47
prim_generic_clock_mux2 68.52 100.00 55.56 50.00
chip_earlgrey_asic 68.94 66.67 50.00 90.14
usbdev_aon_wake 69.61 60.00 65.79 52.63 100.00
prim_subreg_arb 69.80 50.00 59.40 100.00
prim_subreg_arb 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 ) 50.00 50.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 ) 70.00 70.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=32,SwAccess=3,Mubi=0 + DW=3,SwAccess=3,Mubi=0 + DW=10,SwAccess=3,Mubi=0 + DW=5,SwAccess=3,Mubi=0 + DW=8,SwAccess=3,Mubi=0 + DW=2,SwAccess=3,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=1,SwAccess=4,Mubi=0 ) 25.00 0.00 50.00
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 ) 50.00 50.00
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 + DW=16,SwAccess=5,Mubi=0 ) 50.00 50.00
prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 ) 50.00 50.00
prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 ) 50.00 50.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 ) 50.00 50.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 + DW=1,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=24,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=1 + DW=12,SwAccess=0,Mubi=0 + DW=31,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=6,SwAccess=0,Mubi=0 + DW=11,SwAccess=0,Mubi=0 + DW=5,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=27,SwAccess=0,Mubi=0 + DW=20,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=32,SwAccess=1,Mubi=0 + DW=1,SwAccess=1,Mubi=0 + DW=5,SwAccess=1,Mubi=0 + DW=9,SwAccess=1,Mubi=0 + DW=8,SwAccess=1,Mubi=0 + DW=3,SwAccess=1,Mubi=0 + DW=6,SwAccess=1,Mubi=0 + DW=4,SwAccess=1,Mubi=0 + DW=2,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 + DW=20,SwAccess=1,Mubi=0 ) 50.00 50.00
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 ) 42.86 42.86
prim_subreg_arb ( parameter DW=4,SwAccess=4,Mubi=1 ) 25.00 0.00 50.00
prim_subreg_arb ( parameter DW=6,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 ) 100.00 100.00
prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 ) 50.00 50.00
rom_ctrl 77.14 77.14
prim_subreg_ext 80.00 80.00
tlul_err 80.38 96.15 62.86 62.50 100.00
tlul_adapter_reg 85.06 97.37 57.14 85.71 100.00
prim_intr_hw 89.58 100.00 58.33 100.00 100.00
tlul_rsp_intg_gen 91.67 83.33 100.00
tlul_rsp_intg_gen 100.00 100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 ) 66.67 66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 ) 100.00 100.00
prim_subreg 91.67 100.00 75.00 100.00
prim_subreg 100.00 100.00 100.00
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL,Mubi=0 + DW=1,SwAccess=3,RESVAL,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=4,RESVAL=0,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=1,RESVAL=0,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL,Mubi=0 + DW=3,SwAccess=3,RESVAL=0,Mubi=0 ) 50.00 50.00
prim_subreg ( parameter DW=32,SwAccess=1,RESVAL,Mubi=0 + DW=32,SwAccess=0,RESVAL,Mubi + DW=32,SwAccess=3,RESVAL=0,Mubi=0 ) 50.00 50.00
prim_subreg ( parameter DW=4,SwAccess=0,RESVAL,Mubi + DW=4,SwAccess=1,RESVAL=0,Mubi=0 + DW=4,SwAccess=3,RESVAL=9,Mubi=1 + DW=4,SwAccess=4,RESVAL=9,Mubi=1 ) 50.00 50.00
prim_subreg ( parameter DW=6,SwAccess=0,RESVAL,Mubi=0 + DW=6,SwAccess=1,RESVAL=0,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=7,SwAccess=0,RESVAL,Mubi=0 ) 100.00 100.00
prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 + DW=8,SwAccess=1,RESVAL,Mubi=0 + DW=8,SwAccess=3,RESVAL=0,Mubi=0 ) 50.00 50.00
clk_ctrl_and_main_pd_sva_if 92.86 92.86
tlul_rsp_intg_chk 93.33 100.00 80.00 100.00
prim_edge_detector 94.44 100.00 83.33 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
tlul_cmd_intg_gen 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
prim_filter 100.00 100.00 100.00 100.00
prim_generic_buf 100.00 100.00
prim_fifo_sync 100.00 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_generic_pad_wrapper 100.00 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 ) 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 ) 100.00 100.00 100.00 100.00
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 ) 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
prim_mubi4_sync 100.00 100.00
pinmux_jtag_buf
prim_usb_diff_rx
prim_clock_buf
tlul_data_integ_enc
prim_reg_we_check
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