Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3568990	1			T69	1626		T70	83		T76	122
values[2]	717891	1			T69	463		T70	17		T76	54
values[3]	106582	1			T69	24		T70	20		T76	9
values[4]	56265	1			T70	1		T77	2		T329	11
values[5]	37371	1			T329	11		T701	66		T522	10
values[6]	27131	1			T329	11		T701	53		T522	10
values[7]	21175	1			T329	11		T701	52		T522	10
values[8]	17884	1			T329	11		T701	61		T522	10
values[9]	15763	1			T329	11		T701	57		T522	10
values[10]	14567	1			T329	11		T701	57		T522	10
values[11]	13808	1			T329	11		T701	72		T522	10
values[12]	12863	1			T329	11		T701	84		T522	10
values[13]	12101	1			T329	11		T701	83		T522	10
values[14]	11585	1			T329	11		T701	66		T522	10
values[15]	11006	1			T329	11		T701	44		T522	10
values[16]	10670	1			T329	11		T701	57		T522	10
values[17]	10251	1			T329	11		T701	56		T522	10
values[18]	10036	1			T329	11		T701	58		T522	10
values[19]	9578	1			T329	11		T701	41		T522	10
values[20]	9192	1			T329	11		T701	48		T522	10
values[21]	9103	1			T329	11		T701	56		T522	10
values[22]	8826	1			T329	12		T701	28		T522	10
values[23]	8652	1			T329	11		T701	41		T522	11
values[24]	8341	1			T329	11		T701	49		T522	10
values[25]	8061	1			T329	11		T701	63		T522	10
values[26]	7756	1			T329	11		T701	66		T522	10
values[27]	7497	1			T329	11		T701	73		T522	10
values[28]	7183	1			T329	11		T701	57		T522	10
values[29]	6447	1			T329	11		T701	29		T522	10
values[30]	6094	1			T329	11		T701	16		T522	10
values[31]	5608	1			T329	11		T701	22		T522	10
values[32]	5262	1			T329	11		T701	23		T522	10
values[33]	4969	1			T329	11		T701	11		T522	10
values[34]	4681	1			T329	11		T701	15		T522	11
values[35]	4414	1			T329	11		T701	6		T522	11
values[36]	4352	1			T329	11		T701	18		T522	10
values[37]	3900	1			T329	11		T701	11		T522	10
values[38]	3795	1			T329	11		T701	18		T522	10
values[39]	3710	1			T329	11		T701	9		T522	10
values[40]	3519	1			T329	11		T701	4		T522	10
values[41]	3492	1			T329	11		T701	2		T522	11
values[42]	3350	1			T329	11		T701	1		T522	10
values[43]	3311	1			T329	12		T522	11		T521	2
values[44]	3244	1			T329	11		T522	10		T521	4
values[45]	3227	1			T329	11		T522	10		T521	3
values[46]	3107	1			T329	11		T522	10		T521	3
values[47]	2971	1			T329	11		T522	12		T521	4
values[48]	2956	1			T329	11		T522	10		T521	1
values[49]	2947	1			T329	11		T522	10		T521	1
values[50]	2820	1			T329	11		T522	11		T521	1
values[51]	2733	1			T329	11		T522	10		T521	1
values[52]	2766	1			T329	11		T522	10		T521	1
values[53]	2691	1			T329	11		T522	10		T521	1
values[54]	2601	1			T329	11		T522	10		T521	3
values[55]	2588	1			T329	11		T522	11		T521	1
values[56]	2536	1			T329	11		T522	10		T521	2
values[57]	2557	1			T329	11		T522	11		T521	1
values[58]	2540	1			T329	12		T522	10		T521	6
values[59]	2386	1			T329	11		T522	10		T521	4
values[60]	2445	1			T329	11		T522	10		T521	4
values[61]	2784	1			T329	11		T522	10		T521	6
values[62]	4250	1			T329	11		T522	10		T521	11
values[63]	15527	1			T329	11		T522	32		T521	28
values[64]	237218	1			T329	2127		T522	1842		T521	60

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4598359	1			T69	2000		T70	136		T76	77
values[2]	761900	1			T69	437		T70	42		T76	18
values[3]	75520	1			T69	37		T70	12		T77	8
values[4]	13692	1			T69	1		T70	2		T77	1
values[5]	5088	1			T329	21		T522	11		T431	3
values[6]	3069	1			T329	4		T522	7		T521	37
values[7]	2300	1			T329	3		T522	2		T521	25
values[8]	1838	1			T329	1		T522	1		T521	14
values[9]	1598	1			T329	1		T522	1		T521	12
values[10]	1559	1			T329	1		T522	1		T521	6
values[11]	1454	1			T329	1		T522	1		T521	16
values[12]	1397	1			T329	1		T522	1		T521	20
values[13]	1252	1			T329	1		T522	1		T521	15
values[14]	1137	1			T329	1		T522	1		T521	9
values[15]	1140	1			T329	1		T522	1		T521	13
values[16]	1071	1			T329	1		T522	1		T521	9
values[17]	1045	1			T329	1		T522	1		T521	9
values[18]	906	1			T329	1		T522	1		T521	5
values[19]	775	1			T329	1		T522	1		T521	17
values[20]	783	1			T329	1		T522	1		T521	8
values[21]	694	1			T329	1		T522	1		T521	3
values[22]	711	1			T329	1		T522	1		T521	3
values[23]	683	1			T329	1		T522	1		T521	3
values[24]	702	1			T329	1		T522	1		T521	3
values[25]	588	1			T329	1		T522	1		T521	9
values[26]	554	1			T329	1		T522	1		T521	3
values[27]	536	1			T329	1		T522	1		T521	1
values[28]	538	1			T329	1		T522	1		T521	9
values[29]	496	1			T329	1		T522	1		T521	11
values[30]	462	1			T329	1		T522	1		T521	3
values[31]	502	1			T329	1		T522	1		T521	1
values[32]	439	1			T329	1		T522	1		T443	4
values[33]	506	1			T329	1		T522	1		T443	1
values[34]	469	1			T329	1		T522	1		T443	1
values[35]	482	1			T329	1		T522	1		T443	1
values[36]	434	1			T329	1		T522	1		T443	1
values[37]	451	1			T329	1		T522	1		T443	1
values[38]	432	1			T329	1		T522	1		T443	1
values[39]	391	1			T329	1		T522	1		T443	1
values[40]	401	1			T329	1		T522	1		T443	2
values[41]	383	1			T329	1		T522	1		T443	1
values[42]	359	1			T329	1		T522	1		T443	2
values[43]	358	1			T329	1		T522	1		T443	1
values[44]	387	1			T329	1		T522	1		T443	2
values[45]	370	1			T329	1		T522	1		T443	1
values[46]	352	1			T329	1		T522	1		T443	1
values[47]	331	1			T329	1		T522	1		T443	1
values[48]	335	1			T329	1		T522	2		T443	1
values[49]	333	1			T329	1		T522	1		T443	3
values[50]	328	1			T329	1		T522	1		T443	1
values[51]	328	1			T329	1		T522	1		T443	3
values[52]	322	1			T329	1		T522	1		T443	3
values[53]	305	1			T329	1		T522	1		T443	2
values[54]	342	1			T329	1		T522	1		T443	1
values[55]	297	1			T329	1		T522	1		T443	1
values[56]	293	1			T329	1		T522	1		T443	1
values[57]	291	1			T329	1		T522	1		T443	1
values[58]	280	1			T329	1		T522	1		T443	1
values[59]	280	1			T329	1		T522	1		T443	2
values[60]	291	1			T329	1		T522	1		T443	1
values[61]	332	1			T329	1		T522	1		T443	3
values[62]	533	1			T329	1		T522	1		T443	5
values[63]	2532	1			T329	14		T522	1		T443	48
values[64]	21918	1			T329	168		T522	196		T443	97

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	605695	1			T69	19		T70	1		T76	4
values[2]	2477272	1			T69	559		T70	81		T76	56
values[3]	1128266	1			T69	1767		T70	45		T76	29
values[4]	149250	1			T69	71		T76	3		T77	52
values[5]	76312	1			T77	4		T329	11		T701	98
values[6]	49575	1			T329	11		T701	62		T522	10
values[7]	36102	1			T329	11		T701	105		T522	10
values[8]	27826	1			T329	11		T701	92		T522	10
values[9]	23065	1			T329	11		T701	50		T522	10
values[10]	20572	1			T329	12		T701	60		T522	10
values[11]	18339	1			T329	11		T701	58		T522	10
values[12]	16680	1			T329	11		T701	61		T522	10
values[13]	15688	1			T329	11		T701	56		T522	10
values[14]	14550	1			T329	11		T701	61		T522	10
values[15]	13703	1			T329	11		T701	75		T522	10
values[16]	12865	1			T329	11		T701	72		T522	10
values[17]	12540	1			T329	11		T701	66		T522	10
values[18]	12295	1			T329	11		T701	62		T522	11
values[19]	11450	1			T329	11		T701	59		T522	10
values[20]	10985	1			T329	11		T701	65		T522	10
values[21]	10683	1			T329	11		T701	59		T522	10
values[22]	10269	1			T329	11		T701	75		T522	10
values[23]	9987	1			T329	11		T701	58		T522	10
values[24]	9613	1			T329	11		T701	47		T522	10
values[25]	9074	1			T329	12		T701	38		T522	10
values[26]	8557	1			T329	11		T701	45		T522	10
values[27]	8164	1			T329	11		T701	37		T522	11
values[28]	7788	1			T329	11		T701	37		T522	10
values[29]	7473	1			T329	11		T701	26		T522	10
values[30]	6902	1			T329	12		T701	38		T522	10
values[31]	6322	1			T329	11		T701	26		T522	10
values[32]	5887	1			T329	11		T701	35		T522	10
values[33]	5541	1			T329	11		T701	40		T522	10
values[34]	5241	1			T329	13		T701	27		T522	10
values[35]	4973	1			T329	11		T701	21		T522	10
values[36]	4665	1			T329	11		T701	17		T522	10
values[37]	4397	1			T329	11		T701	19		T522	10
values[38]	4059	1			T329	11		T701	16		T522	11
values[39]	3965	1			T329	11		T701	6		T522	11
values[40]	3826	1			T329	11		T701	5		T522	10
values[41]	3678	1			T329	11		T701	4		T522	10
values[42]	3568	1			T329	11		T701	10		T522	10
values[43]	3433	1			T329	11		T701	7		T522	10
values[44]	3490	1			T329	11		T701	8		T522	10
values[45]	3394	1			T329	12		T701	1		T522	10
values[46]	3345	1			T329	11		T701	3		T522	10
values[47]	3310	1			T329	11		T701	1		T522	10
values[48]	3165	1			T329	12		T701	5		T522	10
values[49]	3170	1			T329	11		T701	1		T522	10
values[50]	3103	1			T329	11		T701	2		T522	11
values[51]	3027	1			T329	11		T522	10		T521	4
values[52]	2976	1			T329	11		T522	10		T521	3
values[53]	2984	1			T329	12		T522	11		T521	4
values[54]	2897	1			T329	11		T522	10		T521	2
values[55]	2863	1			T329	12		T522	10		T521	1
values[56]	2800	1			T329	11		T522	10		T521	4
values[57]	2787	1			T329	11		T522	10		T521	1
values[58]	2816	1			T329	11		T522	10		T521	1
values[59]	2820	1			T329	11		T522	10		T521	1
values[60]	2746	1			T329	11		T522	10		T521	3
values[61]	2859	1			T329	12		T522	10		T521	2
values[62]	4101	1			T329	11		T522	11		T521	16
values[63]	19453	1			T329	183		T522	16		T521	31
values[64]	223860	1			T329	1829		T522	1904		T521	46