Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1575427	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

25054364

1

T1

12915

T2

5801

T3

10506

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17373190	1			T1	9429		T2	2100		T3	4208
values[0x0]	7960239	1			T1	3486		T2	3701		T3	6298
values[0x1]	1296362	1			T1	116		T2	160		T3	718

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	476848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26152943

1

T1

13031

T2

5961

T3

11224

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12314887	1			T1	6516		T2	2981		T3	5613
valid_sources[0x01]	12314064	1			T1	6515		T2	2980		T3	5611
valid_sources[0x02]	31436	1			T71	25		T520	19		T168	78
valid_sources[0x03]	31884	1			T71	14		T520	27		T168	75
valid_sources[0x04]	35682	1			T75	2		T71	22		T520	28
valid_sources[0x05]	31659	1			T410	1		T71	13		T520	19
valid_sources[0x06]	32279	1			T409	1		T410	1		T71	16
valid_sources[0x07]	32128	1			T75	12		T71	17		T520	22
valid_sources[0x08]	32146	1			T71	10		T520	19		T168	91
valid_sources[0x09]	31993	1			T409	2		T71	19		T520	23
valid_sources[0x0a]	32771	1			T71	17		T520	22		T168	77
valid_sources[0x0b]	32090	1			T75	4		T410	1		T71	20
valid_sources[0x0c]	32060	1			T75	1		T409	2		T410	1
valid_sources[0x0d]	32300	1			T409	1		T410	1		T71	17
valid_sources[0x0e]	31983	1			T71	11		T520	27		T168	84
valid_sources[0x0f]	32899	1			T410	1		T71	14		T520	23
valid_sources[0x10]	31455	1			T409	1		T71	11		T520	22
valid_sources[0x11]	32600	1			T409	1		T71	11		T520	22
valid_sources[0x12]	32065	1			T410	3		T71	12		T520	29
valid_sources[0x13]	31460	1			T409	1		T410	1		T71	13
valid_sources[0x14]	32618	1			T409	1		T410	1		T71	17
valid_sources[0x15]	32127	1			T409	2		T71	15		T520	21
valid_sources[0x16]	31796	1			T409	1		T71	28		T520	16
valid_sources[0x17]	31494	1			T409	1		T71	15		T520	18
valid_sources[0x18]	32068	1			T410	2		T71	13		T520	24
valid_sources[0x19]	31804	1			T75	5		T71	13		T520	22
valid_sources[0x1a]	33287	1			T75	1		T71	16		T520	23
valid_sources[0x1b]	31617	1			T409	1		T410	1		T71	17
valid_sources[0x1c]	32024	1			T409	2		T410	2		T71	16
valid_sources[0x1d]	31568	1			T409	1		T71	15		T520	32
valid_sources[0x1e]	32038	1			T409	1		T410	1		T71	20
valid_sources[0x1f]	31215	1			T71	9		T520	18		T168	61
valid_sources[0x20]	32563	1			T409	1		T410	2		T71	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16870683

1

T1

9429

T2

2100

T3

4208

values[0x0]

all_enables

biggest_size

7915913

1

T1

3486

T2

3701

T3

6298

values[0x1]

all_enables

biggest_size

267768

1

T72

17

T74

22

T75

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2815132	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

445433

1

T69

281

T70

19

T76

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1104036	1			T69	711		T70	49		T76	57
values[0x0]	1053449	1			T69	662		T70	38		T76	61
values[0x1]	1103080	1			T69	740		T70	34		T76	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2179072	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1081493

1

T69

702

T70

43

T76

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50841	1			T69	28		T77	1		T329	52
valid_sources[0x01]	51585	1			T69	41		T76	2		T77	4
valid_sources[0x02]	52005	1			T69	33		T76	5		T329	40
valid_sources[0x03]	50631	1			T69	33		T77	6		T329	47
valid_sources[0x04]	51849	1			T69	24		T329	45		T78	32
valid_sources[0x05]	52169	1			T69	34		T70	2		T329	49
valid_sources[0x06]	51418	1			T69	44		T329	41		T78	10
valid_sources[0x07]	50521	1			T69	24		T70	4		T329	40
valid_sources[0x08]	51170	1			T69	33		T70	7		T76	5
valid_sources[0x09]	50404	1			T69	40		T76	2		T329	47
valid_sources[0x0a]	50490	1			T69	45		T70	9		T76	4
valid_sources[0x0b]	51125	1			T69	28		T70	4		T76	1
valid_sources[0x0c]	51542	1			T69	30		T329	46		T78	6
valid_sources[0x0d]	51857	1			T69	31		T77	1		T329	43
valid_sources[0x0e]	50526	1			T69	30		T70	4		T76	14
valid_sources[0x0f]	51046	1			T69	30		T329	54		T78	16
valid_sources[0x10]	51390	1			T69	21		T70	4		T77	8
valid_sources[0x11]	51356	1			T69	26		T76	15		T329	43
valid_sources[0x12]	51342	1			T69	39		T70	7		T77	2
valid_sources[0x13]	50779	1			T69	37		T76	4		T77	1
valid_sources[0x14]	51736	1			T69	31		T70	3		T76	1
valid_sources[0x15]	51245	1			T69	29		T70	4		T76	2
valid_sources[0x16]	52207	1			T69	34		T76	1		T77	20
valid_sources[0x17]	51677	1			T69	25		T70	14		T76	6
valid_sources[0x18]	51209	1			T69	41		T70	10		T77	1
valid_sources[0x19]	49099	1			T69	40		T76	4		T329	60
valid_sources[0x1a]	50562	1			T69	37		T76	6		T329	44
valid_sources[0x1b]	51640	1			T69	31		T76	8		T329	40
valid_sources[0x1c]	51114	1			T69	39		T329	43		T463	41
valid_sources[0x1d]	50597	1			T69	27		T77	1		T329	47
valid_sources[0x1e]	49868	1			T69	31		T76	2		T329	41
valid_sources[0x1f]	51674	1			T69	33		T329	50		T78	39
valid_sources[0x20]	50535	1			T69	27		T76	1		T329	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46542

1

T69

29

T70

2

T76

1

values[0x0]

all_enables

biggest_size

352142

1

T69

221

T70

15

T76

18

values[0x1]

all_enables

biggest_size

46749

1

T69

31

T70

2

T76

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2992379	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

486995

1

T69

329

T70

23

T76

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1190582	1			T69	798		T70	69		T76	34
values[0x0]	1097543	1			T69	793		T70	57		T76	22
values[0x1]	1191249	1			T69	884		T70	66		T76	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2296438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1182936

1

T69

849

T70

63

T76

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53843	1			T69	24		T70	3		T76	1
valid_sources[0x01]	54608	1			T69	35		T70	4		T76	17
valid_sources[0x02]	54218	1			T69	30		T70	1		T76	2
valid_sources[0x03]	53619	1			T69	36		T70	8		T77	2
valid_sources[0x04]	54214	1			T69	43		T329	32		T78	49
valid_sources[0x05]	54223	1			T69	51		T70	2		T77	3
valid_sources[0x06]	53775	1			T69	36		T70	2		T77	5
valid_sources[0x07]	54187	1			T69	46		T70	2		T77	3
valid_sources[0x08]	54205	1			T69	52		T70	1		T76	12
valid_sources[0x09]	54267	1			T69	35		T70	1		T77	2
valid_sources[0x0a]	54849	1			T69	37		T70	4		T77	3
valid_sources[0x0b]	54803	1			T69	40		T70	3		T76	4
valid_sources[0x0c]	54327	1			T69	36		T70	4		T77	2
valid_sources[0x0d]	53967	1			T69	39		T70	3		T76	1
valid_sources[0x0e]	55605	1			T69	36		T70	3		T76	1
valid_sources[0x0f]	54232	1			T69	44		T70	5		T77	2
valid_sources[0x10]	55096	1			T69	49		T70	1		T77	1
valid_sources[0x11]	53697	1			T69	43		T70	6		T329	42
valid_sources[0x12]	54796	1			T69	41		T76	2		T329	47
valid_sources[0x13]	54543	1			T69	46		T70	1		T76	2
valid_sources[0x14]	54463	1			T69	41		T70	1		T329	40
valid_sources[0x15]	55508	1			T69	34		T70	4		T77	3
valid_sources[0x16]	55041	1			T69	44		T70	8		T76	2
valid_sources[0x17]	55086	1			T69	53		T70	1		T76	5
valid_sources[0x18]	53890	1			T69	35		T70	5		T77	4
valid_sources[0x19]	53596	1			T69	44		T70	5		T77	5
valid_sources[0x1a]	53861	1			T69	35		T70	2		T76	2
valid_sources[0x1b]	54661	1			T69	39		T70	2		T77	3
valid_sources[0x1c]	54152	1			T69	32		T70	5		T76	6
valid_sources[0x1d]	55152	1			T69	30		T70	2		T77	3
valid_sources[0x1e]	54273	1			T69	33		T76	3		T77	5
valid_sources[0x1f]	54952	1			T69	26		T70	5		T329	45
valid_sources[0x20]	53639	1			T69	32		T70	5		T77	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51109

1

T69

30

T70

3

T76

3

values[0x0]

all_enables

biggest_size

384723

1

T69

278

T70

16

T76

9

values[0x1]

all_enables

biggest_size

51163

1

T69

21

T70

4

T76

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2837266	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

450137

1

T69

323

T70

15

T76

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1112421	1			T69	796		T70	47		T76	35
values[0x0]	1063054	1			T69	760		T70	45		T76	23
values[0x1]	1111928	1			T69	860		T70	35		T76	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2197341	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1090062

1

T69

788

T70

33

T76

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51198	1			T69	47		T77	3		T329	39
valid_sources[0x01]	50937	1			T69	39		T77	2		T329	40
valid_sources[0x02]	50972	1			T69	34		T70	4		T76	1
valid_sources[0x03]	50997	1			T69	48		T77	4		T329	46
valid_sources[0x04]	51744	1			T69	39		T70	3		T77	3
valid_sources[0x05]	52673	1			T69	31		T70	3		T77	4
valid_sources[0x06]	51229	1			T69	31		T70	3		T77	2
valid_sources[0x07]	51712	1			T69	25		T77	3		T329	49
valid_sources[0x08]	51357	1			T69	45		T77	3		T329	42
valid_sources[0x09]	49907	1			T69	27		T70	1		T76	2
valid_sources[0x0a]	51765	1			T69	39		T70	2		T76	6
valid_sources[0x0b]	51488	1			T69	48		T70	7		T77	4
valid_sources[0x0c]	52707	1			T69	41		T76	4		T77	3
valid_sources[0x0d]	51911	1			T69	35		T70	2		T77	4
valid_sources[0x0e]	51068	1			T69	37		T70	7		T77	5
valid_sources[0x0f]	50967	1			T69	28		T329	38		T78	26
valid_sources[0x10]	51205	1			T69	37		T70	3		T76	5
valid_sources[0x11]	51064	1			T69	35		T70	3		T77	2
valid_sources[0x12]	51264	1			T69	25		T70	2		T77	2
valid_sources[0x13]	51329	1			T69	51		T70	4		T77	2
valid_sources[0x14]	51547	1			T69	48		T70	1		T76	1
valid_sources[0x15]	51820	1			T69	30		T77	5		T329	42
valid_sources[0x16]	51725	1			T69	42		T70	5		T76	2
valid_sources[0x17]	51616	1			T69	50		T70	2		T329	41
valid_sources[0x18]	52216	1			T69	33		T77	2		T329	36
valid_sources[0x19]	50320	1			T69	45		T77	5		T329	46
valid_sources[0x1a]	50653	1			T69	40		T70	1		T76	4
valid_sources[0x1b]	52752	1			T69	46		T77	4		T329	44
valid_sources[0x1c]	51787	1			T69	39		T70	1		T76	3
valid_sources[0x1d]	51113	1			T69	38		T70	9		T76	8
valid_sources[0x1e]	50427	1			T69	26		T70	1		T77	3
valid_sources[0x1f]	51599	1			T69	33		T77	1		T329	54
valid_sources[0x20]	51243	1			T69	40		T70	3		T77	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47361

1

T69

30

T70

3

T76

2

values[0x0]

all_enables

biggest_size

355839

1

T69

258

T70

11

T76

12

values[0x1]

all_enables

biggest_size

46937

1

T69

35

T70

1

T76

2