Unified Coverage Report :: Module :: csrng

Module : csrng

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.72			99.72

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_csrng_0.1/rtl/csrng.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_csrng	99.72			99.72

---

Module Instance : tb.dut.top_earlgrey.u_csrng

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.72			99.72

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.72			99.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : csrng

	Total	Covered	Percent
Totals	65	62	95.38
Total Bits	1782	1777	99.72
Total Bits 0->1	891	889	99.78
Total Bits 1->0	891	888	99.66

Ports	65	62	95.38
Port Bits	1782	1777	99.72
Port Bits 0->1	891	889	99.78
Port Bits 1->0	891	888	99.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T69,*T77,*T78	Yes	T69,T77,T78	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T72,*T74,*T165	Yes	T72,T74,T165	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T32	Yes	T1,T2,T3	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T72,*T74,*T165	Yes	T72,T74,T165	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T83,*T103	Yes	T1,T83,T103	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
otp_en_csrng_sw_app_read_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T3,T32,T4	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
entropy_src_hw_if_o.es_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
entropy_src_hw_if_i.es_fips	Yes	Yes	T330,T331,T332	Yes	T1,T83,T103	INPUT
entropy_src_hw_if_i.es_bits[383:0]	Yes	Yes	T1,T83,T103	Yes	T1,T103,T104	INPUT
entropy_src_hw_if_i.es_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cs_aes_halt_i.cs_aes_halt_req	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	INPUT
cs_aes_halt_o.cs_aes_halt_ack	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
csrng_cmd_i[0].genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i[0].csrng_req_bus[31:0]	Yes	Yes	T1,T3,T32	Yes	T1,T2,T3	INPUT
csrng_cmd_i[0].csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i[1].genbits_ready	Yes	Yes	T1,T103,T104	Yes	T1,T103,T104	INPUT
csrng_cmd_i[1].csrng_req_bus[31:0]	Yes	Yes	T1,T103,T104	Yes	T1,T103,T104	INPUT
csrng_cmd_i[1].csrng_req_valid	Yes	Yes	T1,T103,T104	Yes	T1,T103,T104	INPUT
csrng_cmd_o[0].genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o[0].genbits_fips	Yes	Yes	T330,T331,T332	Yes	T103,T104,T105	OUTPUT
csrng_cmd_o[0].genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o[0].csrng_rsp_sts	No	No		No		OUTPUT
csrng_cmd_o[0].csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o[0].csrng_req_ready	Yes	Yes	T1,T147,T148	Yes	T1,T147,T148	OUTPUT
csrng_cmd_o[1].genbits_bus[127:0]	Yes	Yes	T103,T104,T105	Yes	T1,T103,T104	OUTPUT
csrng_cmd_o[1].genbits_fips	No	No		Yes	T330,T331,T332	OUTPUT
csrng_cmd_o[1].genbits_valid	Yes	Yes	T1,T103,T104	Yes	T1,T103,T104	OUTPUT
csrng_cmd_o[1].csrng_rsp_sts	No	No		No		OUTPUT
csrng_cmd_o[1].csrng_rsp_ack	Yes	Yes	T1,T103,T104	Yes	T1,T103,T104	OUTPUT
csrng_cmd_o[1].csrng_req_ready	Yes	Yes	T147,T148,T140	Yes	T147,T148,T140	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T80,T676,T677	Yes	T80,T676,T677	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T80,T82,T114	Yes	T80,T82,T114	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T80,T82,T114	Yes	T80,T82,T114	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T80,T676,T677	Yes	T80,T676,T677	OUTPUT
intr_cs_cmd_req_done_o	Yes	Yes	T284,T288,T295	Yes	T284,T288,T295	OUTPUT
intr_cs_entropy_req_o	Yes	Yes	T284,T297,T298	Yes	T284,T297,T298	OUTPUT
intr_cs_hw_inst_exc_o	Yes	Yes	T284,T288,T295	Yes	T284,T288,T295	OUTPUT
intr_cs_fatal_err_o	Yes	Yes	T284,T288,T295	Yes	T284,T288,T295	OUTPUT

*Tests covering at least one bit in the range