Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T62	Yes	T39,T4,T62	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T39,T4,T62	Yes	T39,T4,T62	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T72,*T73	Yes	T55,T72,T73	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T39,T4,T62	Yes	T39,T4,T62	INPUT
tl_o.a_ready	Yes	Yes	T39,T4,T99	Yes	T39,T4,T99	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T99,T6	Yes	T4,T99,T6	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T99,T6	Yes	T39,T4,T99	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T99,T6	Yes	T39,T4,T99	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T165,*T69	Yes	T74,T165,T69	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T99,*T6	Yes	T4,T99,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T39,T4,T99	Yes	T39,T4,T99	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T32,T172,T684	Yes	T32,T172,T684	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T698	Yes	T80,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T698	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T32,T172,T684	Yes	T32,T172,T684	OUTPUT
cio_rx_i	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T4,T99,T6	Yes	T4,T99,T6	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T99,T92,T285	Yes	T99,T92,T285	OUTPUT
intr_rx_watermark_o	Yes	Yes	T99,T92,T285	Yes	T99,T92,T285	OUTPUT
intr_tx_empty_o	Yes	Yes	T99,T92,T285	Yes	T99,T92,T285	OUTPUT
intr_rx_overflow_o	Yes	Yes	T99,T92,T285	Yes	T99,T92,T285	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T62	Yes	T39,T4,T62	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T39,T4,T62	Yes	T39,T4,T62	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T72,*T73	Yes	T55,T72,T73	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T39,T4,T62	Yes	T39,T4,T62	INPUT
tl_o.a_ready	Yes	Yes	T39,T4,T6	Yes	T39,T4,T6	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T38	Yes	T4,T6,T38	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T38	Yes	T39,T4,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T6,T38	Yes	T39,T4,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T69,*T70	Yes	T74,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T38	Yes	T4,T6,T38	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T39,T4,T6	Yes	T39,T4,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T684,T117,T80	Yes	T684,T117,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T114	Yes	T80,T82,T114	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T114	Yes	T80,T82,T114	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T684,T117,T80	Yes	T684,T117,T80	OUTPUT
cio_rx_i	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T4,T6,T38	Yes	T4,T6,T38	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T285,T187,T188	Yes	T285,T187,T188	OUTPUT
intr_rx_watermark_o	Yes	Yes	T285,T187,T188	Yes	T285,T187,T188	OUTPUT
intr_tx_empty_o	Yes	Yes	T285,T187,T188	Yes	T285,T187,T188	OUTPUT
intr_rx_overflow_o	Yes	Yes	T285,T187,T188	Yes	T285,T187,T188	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T92,T285,T180	Yes	T92,T285,T180	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T92,T285,T180	Yes	T92,T285,T180	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T72,*T73	Yes	T55,T72,T73	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T92,T285,T117	Yes	T92,T285,T117	INPUT
tl_o.a_ready	Yes	Yes	T92,T285,T117	Yes	T92,T285,T117	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T92,T285,T180	Yes	T92,T285,T180	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T92,T285,T117	Yes	T92,T285,T117	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T92,T285,T117	Yes	T92,T285,T117	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T69,*T76	Yes	T74,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T92,*T285,*T180	Yes	T92,T285,T180	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T92,T285,T117	Yes	T92,T285,T117	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T32,T172,T117	Yes	T32,T172,T117	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T114	Yes	T80,T82,T114	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T114	Yes	T80,T82,T114	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T32,T172,T117	Yes	T32,T172,T117	OUTPUT
cio_rx_i	Yes	Yes	T92,T33,T180	Yes	T92,T33,T12	INPUT
cio_tx_o	Yes	Yes	T92,T180,T181	Yes	T92,T180,T181	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T92,T285,T180	Yes	T92,T285,T180	OUTPUT
intr_rx_watermark_o	Yes	Yes	T92,T285,T180	Yes	T92,T285,T180	OUTPUT
intr_tx_empty_o	Yes	Yes	T92,T285,T180	Yes	T92,T285,T180	OUTPUT
intr_rx_overflow_o	Yes	Yes	T92,T285,T180	Yes	T92,T285,T180	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T99,T285,T300	Yes	T99,T285,T300	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T99,T285,T300	Yes	T99,T285,T300	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T72,*T73	Yes	T55,T72,T73	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T99,T285,T117	Yes	T99,T285,T117	INPUT
tl_o.a_ready	Yes	Yes	T99,T285,T117	Yes	T99,T285,T117	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T99,T285,T300	Yes	T99,T285,T300	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T99,T285,T117	Yes	T99,T285,T117	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T99,T285,T117	Yes	T99,T285,T117	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T76,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T74,*T165,*T69	Yes	T74,T165,T69	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T99,*T285,*T300	Yes	T99,T285,T300	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T99,T285,T117	Yes	T99,T285,T117	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T117,T80,T685	Yes	T117,T80,T685	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T114	Yes	T82,T114,T697	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T114,T697	Yes	T80,T82,T114	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T117,T80,T685	Yes	T117,T80,T685	OUTPUT
cio_rx_i	Yes	Yes	T99,T300,T308	Yes	T99,T300,T308	INPUT
cio_tx_o	Yes	Yes	T99,T300,T308	Yes	T99,T300,T308	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T99,T285,T300	Yes	T99,T285,T300	OUTPUT
intr_rx_watermark_o	Yes	Yes	T99,T285,T300	Yes	T99,T285,T300	OUTPUT
intr_tx_empty_o	Yes	Yes	T99,T285,T300	Yes	T99,T285,T300	OUTPUT
intr_rx_overflow_o	Yes	Yes	T99,T285,T300	Yes	T99,T285,T300	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T285,T14,T286	Yes	T285,T14,T286	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T285,T14,T286	Yes	T285,T14,T286	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T55,*T72,*T73	Yes	T55,T72,T73	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_i.a_valid	Yes	Yes	T285,T14,T117	Yes	T285,T14,T117	INPUT
tl_o.a_ready	Yes	Yes	T285,T14,T117	Yes	T285,T14,T117	OUTPUT
tl_o.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T285,T14,T286	Yes	T285,T14,T286	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T285,T14,T117	Yes	T285,T14,T117	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T285,T14,T117	Yes	T285,T14,T117	OUTPUT
tl_o.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T165,*T69,*T329	Yes	T165,T69,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T69,T71,T77	Yes	T69,T70,T71	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T285,*T14,*T286	Yes	T285,T14,T286	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T285,T14,T117	Yes	T285,T14,T117	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T117,T80,T81	Yes	T117,T80,T81	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T81,T698	Yes	T80,T81,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T698	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T117,T80,T81	Yes	T117,T80,T81	OUTPUT
cio_rx_i	Yes	Yes	T14,T286,T287	Yes	T14,T286,T287	INPUT
cio_tx_o	Yes	Yes	T14,T286,T287	Yes	T14,T286,T287	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T285,T14,T286	Yes	T285,T14,T286	OUTPUT
intr_rx_watermark_o	Yes	Yes	T285,T14,T286	Yes	T285,T14,T286	OUTPUT
intr_tx_empty_o	Yes	Yes	T285,T14,T286	Yes	T285,T14,T286	OUTPUT
intr_rx_overflow_o	Yes	Yes	T285,T14,T286	Yes	T285,T14,T286	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T285,T296,T303	Yes	T285,T296,T303	OUTPUT

*Tests covering at least one bit in the range