Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.74	90.68		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T69,T76,T77	Yes	T69,T76,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T32,T202,T203	Yes	T32,T202,T203	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T32,T202,T203	Yes	T32,T202,T203	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T72,T69,T71	Yes	T72,T69,T71	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T32,T58,T204	Yes	T32,T58,T204	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T59,T55,T60	Yes	T59,T55,T60	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T59,T55,T60	Yes	T59,T55,T60	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T59,T55,T60	Yes	T59,T55,T60	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T59,T55,T60	Yes	T59,T55,T60	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T59,T55,T60	Yes	T59,T55,T60	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T59,T55,T60	Yes	T59,T55,T60	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T59,*T55,*T60	Yes	T59,T55,T60	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T59,T55,T60	Yes	T59,T55,T60	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T69,*T70,T76	Yes	T69,T70,T76	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T69,T71,T77	Yes	T69,T71,T77	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T71,T76	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T69,T77,T78	Yes	T69,T76,T77	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T71,T76	Yes	T69,T71,T76	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T69,T71,T76	Yes	T69,T70,T71	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T69,T76,T77	Yes	T69,T70,T76	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T69,T78,T416	Yes	T69,T70,T76	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T69,T71,T77	Yes	T69,T71,T77	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T69,*T77,*T78	Yes	T69,T76,T77	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T74,T191,T192	Yes	T74,T191,T192	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T74,T191,T192	Yes	T74,T191,T192	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T74,T191,T192	Yes	T74,T191,T192	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T74,T191,T192	Yes	T74,T191,T192	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T74,T191,T192	Yes	T74,T191,T192	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T191,*T192,*T193	Yes	T191,T192,T193	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T74,T191,T192	Yes	T74,T191,T192	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T32,T4	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T191,T192,T193	Yes	T191,T192,T193	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T191,T192	Yes	T74,T191,T192	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T3,T32,T4	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T191,*T192,*T193	Yes	T191,T192,T193	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T3,T32,T4	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T74,T191,T192	Yes	T74,T191,T192	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T395,T396,T75	Yes	T395,T396,T75	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T50,T51,T52	Yes	T50,T51,T52	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T243,T397,T398	Yes	T243,T397,T398	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T243,T397,T398	Yes	T243,T397,T398	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T50,T51,T52	Yes	T50,T51,T52	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T243,T397,T398	Yes	T243,T397,T398	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T243,T397,T398	Yes	T243,T397,T398	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T243,T397,T398	Yes	T243,T397,T398	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T243,T398,T399	Yes	T243,T398,T399	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T70,T71	Yes	T50,T51,T52	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T243,T398,T399	Yes	T243,T398,T50	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T69,T70,*T77	Yes	T69,T70,T76	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T243,*T397,*T399	Yes	T243,T397,T398	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T243,T397,T398	Yes	T243,T397,T398	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T55,*T72,*T73	Yes	T55,T72,T73	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T259,T736,T737	Yes	T259,T736,T737	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T55,*T72,*T73	Yes	T55,T72,T73	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T10,T117,T350	Yes	T10,T117,T350	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T117,T110	Yes	T10,T117,T110	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T117,T350	Yes	T10,T117,T350	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T10,T117,T350	Yes	T10,T117,T350	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T117,T110	Yes	T10,T117,T110	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T10,T117,T350	Yes	T10,T117,T350	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T74,*T69,*T70	Yes	T74,T69,T70	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T11,T201	Yes	T10,T11,T201	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T10,T117,T350	Yes	T10,T117,T350	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T10,T117,T350	Yes	T10,T117,T350	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T110,T111	Yes	T10,T110,T111	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T117,T350	Yes	T10,T117,T350	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T110,T111	Yes	T10,T110,T111	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T74,*T69,*T76	Yes	T74,T69,T70	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T350,*T110	Yes	T10,T350,T110	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T10,T117,T350	Yes	T10,T117,T350	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T33,T350,T110	Yes	T33,T350,T110	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T33,T110,T111	Yes	T33,T110,T111	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T33,T350,T110	Yes	T33,T350,T110	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T33,T350,T110	Yes	T33,T350,T110	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T33,T110,T111	Yes	T33,T110,T111	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T33,T350,T110	Yes	T33,T350,T110	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T74,*T69,*T70	Yes	T74,T69,T70	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T69,T71,T76	Yes	T69,T71,T76	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T69,T71,T76	Yes	T69,T71,T76	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T33,T350,T110	Yes	T33,T350,T110	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T33,T350,T110	Yes	T33,T350,T110	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T69,T71,T76	Yes	T69,T70,T71	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T33,T110,T111	Yes	T33,T110,T111	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T350,T110	Yes	T33,T350,T110	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T33,T110,T111	Yes	T33,T110,T111	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T74,*T69,*T76	Yes	T74,T69,T70	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T69,T71,T76	Yes	T69,T71,T76	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T33,*T350,*T110	Yes	T33,T350,T110	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T33,T350,T110	Yes	T33,T350,T110	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T165,*T69,*T76	Yes	T165,T69,T76	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_usbdev_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T285,T350,T20	Yes	T285,T350,T20	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T285,T350,T20	Yes	T285,T350,T20	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T18,T285,T19	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T76,T77	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T165,*T69,*T70	Yes	T165,T69,T70	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T16,*T17,*T18	Yes	T18,T285,T19	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T72,*T69,*T70	Yes	T72,T69,T70	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T32,T4	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T32	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T69,T70,T77	Yes	T69,T70,T77	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T72,*T69,*T77	Yes	T72,T69,T70	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T72,T69,T71	Yes	T72,T69,T71	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T72,T69,T70	Yes	T72,T69,T70	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T77	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T72,T69,T70	Yes	T72,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T72,*T69,*T70	Yes	T72,T69,T76	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T3,T32	Yes	T2,T3,T32	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T32,T4	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T69,*T70,*T71	Yes	T69,T70,T71	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T3,T32,T39	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T39,T84,T4	Yes	T39,T84,T4	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T84,T4	Yes	T39,T84,T4	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T3,T39,T84	Yes	T3,T39,T84	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T39,T84,T4	Yes	T39,T84,T4	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T3,T39,T84	Yes	T3,T39,T84	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T72,*T69,*T70	Yes	T72,T69,T70	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T84,T368,T721	Yes	T84,T368,T721	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T3,T39,T84	Yes	T3,T39,T84	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T3,T39,T84	Yes	T3,T39,T84	INPUT
tl_hmac_i.d_error	Yes	Yes	T69,T71,T76	Yes	T69,T71,T77	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T3,T39,T84	Yes	T3,T39,T84	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T39,T84	Yes	T3,T39,T84	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T39,T84,T4	Yes	T39,T84,T4	INPUT
tl_hmac_i.d_sink	Yes	Yes	T69,T76,T77	Yes	T69,T76,T77	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T72,*T69,*T78	Yes	T72,T69,T70	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T71,T76	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T39,*T84,*T4	Yes	T39,T84,T4	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T3,T39,T84	Yes	T3,T39,T84	INPUT
tl_kmac_o.d_ready	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T413,T365,T414	Yes	T413,T365,T414	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T413,T365,T414	Yes	T413,T365,T414	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T72,*T69,*T70	Yes	T72,T69,T70	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T69,T71,T76	Yes	T69,T71,T76	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T413,T365,T414	Yes	T413,T365,T414	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	INPUT
tl_kmac_i.d_error	Yes	Yes	T69,T71,T76	Yes	T69,T71,T76	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T107,T109,T129	Yes	T413,T365,T414	INPUT
tl_kmac_i.d_sink	Yes	Yes	T69,T76,T77	Yes	T69,T70,T76	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T72,*T69,*T78	Yes	T72,T69,T70	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T69,T71,T76	Yes	T69,T71,T76	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T107,*T109,*T129	Yes	T413,T365,T414	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	INPUT
tl_aes_o.d_ready	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T107,T718,T719	Yes	T107,T718,T719	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T107,T718,T719	Yes	T107,T718,T719	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T107,T718,T719	Yes	T107,T718,T719	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T72,*T74,*T165	Yes	T72,T74,T165	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T69,T71,T76	Yes	T69,T71,T76	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T3,T107,T415	Yes	T3,T107,T415	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T107,T415,T718	Yes	T107,T415,T718	INPUT
tl_aes_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T107,T415,T718	Yes	T107,T415,T718	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T107,T718,T719	Yes	T107,T718,T719	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T107,T415,T718	Yes	T107,T415,T718	INPUT
tl_aes_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T72,*T74,*T165	Yes	T72,T74,T165	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T69,T71,T76	Yes	T69,T70,T71	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T107,*T415,*T718	Yes	T107,T415,T718	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T107,T415,T718	Yes	T107,T415,T718	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T72,*T69,*T70	Yes	T72,T69,T70	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T69,T71,T77	Yes	T69,T71,T77	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T69,T71,T77	Yes	T69,T71,T77	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T32	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T3,T32,T83	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T77	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T72,*T69,*T329	Yes	T72,T69,T76	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T69,T71,T76	Yes	T69,T70,T71	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T1,*T83,*T103	Yes	T1,T83,T39	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T72,*T74,*T165	Yes	T72,T74,T165	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T32	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T3,T32,T4	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T72,*T74,*T165	Yes	T72,T74,T165	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T1,*T83,*T103	Yes	T1,T83,T103	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T72,*T69,*T70	Yes	T72,T69,T70	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T69,T71,T76	Yes	T69,T71,T76	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T32	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T3,T32	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T72,*T69,*T70	Yes	T72,T69,T70	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T1,*T83,*T103	Yes	T1,T83,T103	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T3,T32	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T72,*T69,*T70	Yes	T72,T69,T70	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	INPUT
tl_edn1_i.d_error	Yes	Yes	T69,T71,T77	Yes	T69,T71,T77	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T103,T104	Yes	T1,T83,T103	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T1,T103,T104	Yes	T1,T83,T103	INPUT
tl_edn1_i.d_sink	Yes	Yes	T69,T77,T78	Yes	T69,T77,T78	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T72,*T69,*T78	Yes	T72,T69,T70	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T1,*T83,*T103	Yes	T1,T83,T103	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T1,T83,T103	Yes	T1,T83,T103	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T2,T3,T32	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T2,T32,T57	Yes	T2,T32,T57	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T32,T49	Yes	T2,T32,T49	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T2,T32,T49	Yes	T2,T32,T49	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T2,T32,T49	Yes	T2,T32,T49	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T2,T32,T49	Yes	T2,T32,T49	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T74,*T69,*T70	Yes	T74,T69,T70	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T2,T32,T49	Yes	T2,T32,T49	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T2,T32,T49	Yes	T2,T32,T49	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T2,T32,T57	Yes	T2,T32,T57	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T32,T49	Yes	T2,T32,T49	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T2,T32,T49	Yes	T2,T32,T49	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T74,*T69,*T76	Yes	T74,T69,T70	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T2,*T32,*T49	Yes	T2,T32,T49	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T2,T32,T49	Yes	T2,T32,T49	INPUT
tl_otbn_o.d_ready	Yes	Yes	T3,T32,T39	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T103	Yes	T39,T4,T103	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T39,T4	Yes	T3,T39,T4	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T3,T39,T4	Yes	T3,T39,T4	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T39,T4,T103	Yes	T39,T4,T103	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T3,T39,T4	Yes	T3,T39,T4	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T75,*T409,*T410	Yes	T75,T409,T410	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T3,T39,T4	Yes	T3,T39,T4	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T3,T39,T4	Yes	T3,T39,T4	INPUT
tl_otbn_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T39,T4,T103	Yes	T39,T4,T103	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T39,T4	Yes	T3,T39,T4	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T3,T39,T4	Yes	T3,T39,T4	INPUT
tl_otbn_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T75,*T409,*T410	Yes	T75,T409,T410	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T39,*T4,*T103	Yes	T39,T4,T103	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T3,T39,T4	Yes	T3,T39,T4	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T3,T32,T39	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T39,T62,T107	Yes	T39,T62,T107	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T62,T107	Yes	T39,T62,T107	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T39,T62,T107	Yes	T39,T62,T107	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T62,T107,T63	Yes	T62,T107,T63	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T39,T62,T107	Yes	T39,T62,T107	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T72,*T69,*T70	Yes	T72,T69,T70	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T39,T62,T107	Yes	T39,T62,T107	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T39,T62,T107	Yes	T39,T62,T107	INPUT
tl_keymgr_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T62,T107,T63	Yes	T62,T107,T63	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T62,T107	Yes	T39,T62,T107	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T39,T62,T107	Yes	T39,T62,T107	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T72,*T69,*T78	Yes	T72,T69,T70	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T39,*T62,*T107	Yes	T39,T62,T107	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T39,T62,T107	Yes	T39,T62,T107	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T69,*T70,*T77	Yes	T69,T70,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T32	Yes	T1,T2,T32	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T2,T32	Yes	T1,T2,T32	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T3,T32,T39	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T39,T4,T6	Yes	T39,T4,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T4,T6	Yes	T39,T4,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T39,T4,T6	Yes	T39,T4,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T39,T4,T6	Yes	T39,T4,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T39,T4,T6	Yes	T39,T4,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T74,*T69,*T76	Yes	T74,T69,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T69,T71,T76	Yes	T69,T71,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T39,T4,T6	Yes	T39,T4,T6	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T39,T4,T6	Yes	T39,T4,T6	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T69,T70,T71	Yes	T69,T71,T76	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T74,T69,T70	Yes	T74,T69,T70	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T38	Yes	T39,T4,T6	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T4,T6,T38	Yes	T39,T4,T6	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T76,T77	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T74,T69,*T70	Yes	T74,T69,T70	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T134,*T135,*T136	Yes	T239,T407,T134	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T39,T4,T6	Yes	T39,T4,T6	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T32,T4	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T69,T70,T76	Yes	T69,T70,T76	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range