Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.59 99.59

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn0 99.50 99.50
tb.dut.top_earlgrey.u_edn1 99.58 99.58


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.50 99.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.50 99.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.74 90.68 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.58 99.58


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.58 99.58


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.74 90.68 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1206 1201 99.59
Total Bits 0->1 603 602 99.83
Total Bits 1->0 603 599 99.34

Ports 78 74 94.87
Port Bits 1206 1201 99.59
Port Bits 0->1 603 602 99.83
Port Bits 1->0 603 599 99.34

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T32,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T69,*T70,*T76 Yes T69,T70,T76 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T72,*T69,*T70 Yes T72,T69,T70 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T3,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T3,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T69,T70,T76 Yes T69,T70,T76 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T69,*T70 Yes T72,T69,T70 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T83,*T103 Yes T1,T83,T103 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T62,T103,T107 Yes T62,T103,T107 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T414,T142,T221 Yes T414,T142,T221 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T62,T103,T107 Yes T62,T103,T107 OUTPUT
edn_o[0].edn_fips Yes Yes T147,T148,T140 Yes T103,T104,T105 OUTPUT
edn_o[0].edn_ack Yes Yes T62,T103,T107 Yes T62,T103,T107 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T103,T104,T105 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T3,T32 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_fips Yes Yes T140,T141 Yes T104,T105,T142 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T414,T142,T221 Yes T414,T142,T221 OUTPUT
edn_o[3].edn_fips No No Yes T142,T221,T222 OUTPUT
edn_o[3].edn_ack Yes Yes T414,T142,T221 Yes T414,T142,T221 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T1,T3,T85 Yes T1,T3,T85 OUTPUT
edn_o[4].edn_fips No No Yes T104,T669,T670 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T148,T671,T672 Yes T142,T221,T673 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T147,T148,T140 Yes T103,T104,T105 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T1,T39,T85 Yes T1,T2,T83 OUTPUT
edn_o[7].edn_fips Yes Yes T147,T148,T140 Yes T142,T221,T147 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T3,T32 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T330,T331,T332 Yes T103,T104,T105 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T147,T148 Yes T1,T147,T148 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T1,T80,T72 Yes T1,T80,T72 INPUT
alert_rx_i[0].ping_n Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T49,T367,T80 Yes T49,T367,T80 INPUT
alert_rx_i[1].ping_n Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_rx_i[1].ping_p Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T1,T80,T72 Yes T1,T80,T72 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T49,T367,T80 Yes T49,T367,T80 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T284,T297,T298 Yes T284,T297,T298 OUTPUT
intr_edn_fatal_err_o Yes Yes T284,T288,T295 Yes T284,T288,T295 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 73 93.59
Total Bits 1204 1198 99.50
Total Bits 0->1 602 601 99.83
Total Bits 1->0 602 597 99.17

Ports 78 73 93.59
Port Bits 1204 1198 99.50
Port Bits 0->1 602 601 99.83
Port Bits 1->0 602 597 99.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T32,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T69,*T70,*T76 Yes T69,T70,T76 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T72,*T69,*T70 Yes T72,T69,T70 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T69,T71,T76 Yes T69,T71,T76 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T3,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T3,T32 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Yes Yes T69,T70,T76 Yes T69,T70,T76 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T69,*T70 Yes T72,T69,T70 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T83,*T103 Yes T1,T83,T103 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T62,T107,T63 Yes T62,T107,T63 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T414,T142,T221 Yes T414,T142,T221 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T62,T107,T63 Yes T62,T107,T63 OUTPUT
edn_o[0].edn_fips No No Yes T142,T221,T222 OUTPUT
edn_o[0].edn_ack Yes Yes T62,T107,T63 Yes T62,T107,T63 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T103,T104,T105 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T3,T32 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_fips Yes Yes T140,T141 Yes T104,T105,T142 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T414,T142,T221 Yes T414,T142,T221 OUTPUT
edn_o[3].edn_fips No No Yes T142,T221,T222 OUTPUT
edn_o[3].edn_ack Yes Yes T414,T142,T221 Yes T414,T142,T221 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T1,T3,T85 Yes T1,T3,T85 OUTPUT
edn_o[4].edn_fips No No Yes T104,T669,T670 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T148,T671,T672 Yes T142,T221,T673 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T147,T148,T140 Yes T103,T104,T105 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T1,T39,T85 Yes T1,T2,T83 OUTPUT
edn_o[7].edn_fips Yes Yes T147,T148,T140 Yes T142,T221,T147 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T3,T32 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T330,T331,T332 Yes T103,T104,T105 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T147,T148 Yes T1,T147,T148 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T1,T80,T72 Yes T1,T80,T72 INPUT
alert_rx_i[0].ping_n Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T80,T674,T675 Yes T80,T674,T675 INPUT
alert_rx_i[1].ping_n Yes Yes T80,T82,T114 Yes T80,T82,T114 INPUT
alert_rx_i[1].ping_p Yes Yes T80,T82,T114 Yes T80,T82,T114 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T1,T80,T72 Yes T1,T80,T72 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T80,T674,T675 Yes T80,T674,T675 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T284,T297,T298 Yes T284,T297,T298 OUTPUT
intr_edn_fatal_err_o Yes Yes T284,T288,T295 Yes T284,T288,T295 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 710 707 99.58
Total Bits 0->1 355 354 99.72
Total Bits 1->0 355 353 99.44

Ports 50 48 96.00
Port Bits 710 707 99.58
Port Bits 0->1 355 354 99.72
Port Bits 1->0 355 353 99.44

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T32,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T3,T32 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_i.a_address[6:0] Yes Yes *T69,*T76,*T77 Yes T69,T76,T77 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T83,*T103 Yes T1,T83,T103 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T83,*T103 Yes T1,T83,T103 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T72,*T69,*T70 Yes T72,T69,T70 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 INPUT
tl_i.a_valid Yes Yes T1,T83,T103 Yes T1,T83,T103 INPUT
tl_o.a_ready Yes Yes T1,T83,T103 Yes T1,T83,T103 OUTPUT
tl_o.d_error Yes Yes T69,T71,T77 Yes T69,T71,T77 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T83,T103 Yes T1,T83,T103 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T103,T104 Yes T1,T83,T103 OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T103,T104 Yes T1,T83,T103 OUTPUT
tl_o.d_sink Yes Yes T69,T77,T78 Yes T69,T77,T78 OUTPUT
tl_o.d_source[5:0] Yes Yes *T72,*T69,*T78 Yes T72,T69,T70 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T83,*T103 Yes T1,T83,T103 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T83,T103 Yes T1,T83,T103 OUTPUT
edn_i[0].edn_req Yes Yes T103,T104,T105 Yes T103,T104,T105 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T103,T104,T105 Yes T103,T104,T105 OUTPUT
edn_o[0].edn_fips Yes Yes T147,T148,T140 Yes T103,T104,T105 OUTPUT
edn_o[0].edn_ack Yes Yes T103,T104,T105 Yes T103,T104,T105 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T1,T103,T104 Yes T1,T103,T104 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T103,T104 Yes T1,T103,T104 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T103,T104 Yes T1,T103,T104 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T103,T104,T105 Yes T1,T103,T104 INPUT
csrng_cmd_i.genbits_fips No No Yes T330,T331,T332 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T103,T104 Yes T1,T103,T104 INPUT
csrng_cmd_i.csrng_rsp_sts No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T103,T104 Yes T1,T103,T104 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T147,T148,T140 Yes T147,T148,T140 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T80,T72,T81 Yes T80,T72,T81 INPUT
alert_rx_i[0].ping_n Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T49,T367,T80 Yes T49,T367,T80 INPUT
alert_rx_i[1].ping_n Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_rx_i[1].ping_p Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T80,T72,T81 Yes T80,T72,T81 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T49,T367,T80 Yes T49,T367,T80 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T284,T297,T298 Yes T284,T297,T298 OUTPUT
intr_edn_fatal_err_o Yes Yes T284,T288,T295 Yes T284,T288,T295 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%