Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3656196	1			T66	79		T67	292		T72	823
values[2]	728305	1			T66	239		T67	47		T72	212
values[3]	100934	1			T66	290		T67	2		T74	3
values[4]	53581	1			T66	189		T406	58		T388	10
values[5]	36392	1			T66	125		T406	33		T388	10
values[6]	26995	1			T66	94		T406	14		T388	10
values[7]	21713	1			T66	67		T406	26		T388	10
values[8]	18346	1			T66	40		T406	21		T388	10
values[9]	16156	1			T66	22		T406	27		T388	10
values[10]	15029	1			T66	22		T406	22		T388	10
values[11]	14076	1			T66	22		T406	17		T388	10
values[12]	13140	1			T66	29		T406	28		T388	10
values[13]	12398	1			T66	22		T406	34		T388	10
values[14]	12116	1			T66	28		T406	23		T388	10
values[15]	11321	1			T66	21		T406	15		T388	10
values[16]	10956	1			T66	17		T406	31		T388	10
values[17]	10283	1			T66	24		T406	27		T388	10
values[18]	9768	1			T66	17		T406	30		T388	10
values[19]	9500	1			T66	15		T406	18		T388	10
values[20]	9275	1			T66	14		T406	24		T388	11
values[21]	8922	1			T66	11		T406	20		T388	10
values[22]	8821	1			T66	5		T406	25		T388	10
values[23]	8481	1			T66	4		T406	14		T388	10
values[24]	7983	1			T66	6		T406	27		T388	10
values[25]	7864	1			T66	14		T406	19		T388	10
values[26]	7508	1			T66	9		T406	16		T388	10
values[27]	7078	1			T66	7		T406	11		T388	10
values[28]	6785	1			T66	6		T406	10		T388	10
values[29]	6280	1			T66	4		T406	2		T388	10
values[30]	5965	1			T66	5		T388	11		T498	1
values[31]	5612	1			T66	3		T388	10		T498	1
values[32]	5165	1			T66	7		T388	10		T498	1
values[33]	4877	1			T66	28		T388	10		T498	3
values[34]	4434	1			T66	5		T388	10		T498	2
values[35]	4209	1			T66	1		T388	10		T498	1
values[36]	3964	1			T66	3		T388	10		T498	2
values[37]	3734	1			T66	3		T388	10		T498	5
values[38]	3475	1			T66	1		T388	11		T498	4
values[39]	3373	1			T66	3		T388	10		T498	3
values[40]	3263	1			T66	3		T388	10		T498	4
values[41]	3095	1			T66	1		T388	10		T498	3
values[42]	3053	1			T66	4		T388	10		T498	1
values[43]	2991	1			T66	3		T388	11		T498	1
values[44]	2958	1			T66	2		T388	10		T498	1
values[45]	2904	1			T66	5		T388	10		T498	1
values[46]	2851	1			T66	1		T388	10		T498	3
values[47]	2793	1			T66	3		T388	10		T498	2
values[48]	2751	1			T66	1		T388	10		T495	10
values[49]	2666	1			T66	2		T388	10		T495	6
values[50]	2638	1			T66	2		T388	10		T495	7
values[51]	2619	1			T66	5		T388	10		T495	4
values[52]	2615	1			T66	3		T388	10		T495	5
values[53]	2499	1			T66	1		T388	10		T495	8
values[54]	2344	1			T66	1		T388	10		T495	5
values[55]	2353	1			T66	1		T388	10		T495	3
values[56]	2301	1			T66	5		T388	11		T495	6
values[57]	2350	1			T66	4		T388	10		T495	6
values[58]	2241	1			T66	2		T388	11		T495	7
values[59]	2232	1			T66	2		T388	10		T495	8
values[60]	2317	1			T66	11		T388	10		T495	12
values[61]	2567	1			T66	8		T388	11		T495	8
values[62]	4218	1			T66	10		T388	11		T495	4
values[63]	15267	1			T66	37		T388	14		T495	38
values[64]	215350	1			T66	67		T388	1871		T495	263

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4682844	1			T66	1496		T67	681		T72	889
values[2]	767115	1			T66	361		T67	113		T72	216
values[3]	74514	1			T66	42		T67	9		T72	6
values[4]	13781	1			T66	1		T72	3		T73	2
values[5]	5538	1			T72	1		T388	17		T498	84
values[6]	3378	1			T388	6		T498	65		T507	1
values[7]	2621	1			T388	2		T498	38		T495	19
values[8]	2236	1			T388	2		T498	21		T495	13
values[9]	1980	1			T388	2		T498	2		T495	11
values[10]	1779	1			T388	1		T495	7		T374	6
values[11]	1523	1			T495	8		T374	5		T449	17
values[12]	1310	1			T495	17		T374	3		T449	10
values[13]	1302	1			T495	14		T374	3		T449	8
values[14]	1237	1			T495	15		T374	4		T449	8
values[15]	1145	1			T495	21		T374	4		T449	12
values[16]	1086	1			T495	13		T374	3		T449	12
values[17]	962	1			T495	13		T374	4		T449	10
values[18]	898	1			T495	5		T374	3		T449	12
values[19]	909	1			T495	6		T374	4		T449	11
values[20]	906	1			T374	3		T449	12		T671	9
values[21]	817	1			T374	7		T449	8		T671	10
values[22]	804	1			T374	3		T449	5		T671	9
values[23]	776	1			T374	7		T449	3		T671	3
values[24]	637	1			T374	3		T449	9		T671	5
values[25]	594	1			T374	3		T449	10		T671	5
values[26]	601	1			T374	4		T449	17		T671	3
values[27]	572	1			T374	3		T449	17		T671	1
values[28]	566	1			T374	7		T449	9		T671	6
values[29]	582	1			T374	3		T449	8		T671	1
values[30]	541	1			T374	4		T449	8		T671	4
values[31]	520	1			T374	4		T449	8		T671	11
values[32]	470	1			T374	4		T449	4		T671	5
values[33]	448	1			T374	3		T449	7		T671	5
values[34]	454	1			T374	3		T449	9		T671	1
values[35]	445	1			T374	3		T449	3		T671	1
values[36]	433	1			T374	3		T449	3		T671	1
values[37]	460	1			T374	3		T449	9		T671	6
values[38]	463	1			T374	4		T449	9		T671	4
values[39]	463	1			T374	8		T449	17		T671	7
values[40]	445	1			T374	4		T449	16		T409	2
values[41]	462	1			T374	4		T449	10		T409	1
values[42]	449	1			T374	2		T449	6		T409	6
values[43]	400	1			T374	4		T449	3		T409	6
values[44]	400	1			T374	1		T449	2		T409	5
values[45]	375	1			T374	3		T449	2		T409	1
values[46]	378	1			T374	2		T449	2		T409	4
values[47]	389	1			T374	3		T449	3		T409	1
values[48]	375	1			T374	4		T449	5		T409	2
values[49]	344	1			T374	2		T449	5		T409	3
values[50]	346	1			T374	3		T449	4		T409	1
values[51]	365	1			T374	1		T449	3		T409	2
values[52]	353	1			T374	3		T449	3		T409	1
values[53]	368	1			T374	3		T449	5		T409	2
values[54]	344	1			T374	2		T449	6		T409	1
values[55]	370	1			T374	2		T449	12		T409	2
values[56]	372	1			T374	1		T449	13		T409	1
values[57]	361	1			T374	3		T449	11		T409	3
values[58]	345	1			T374	1		T449	10		T409	1
values[59]	360	1			T374	1		T449	11		T409	1
values[60]	381	1			T374	2		T449	12		T409	1
values[61]	415	1			T374	1		T449	7		T409	2
values[62]	746	1			T374	1		T449	16		T409	1
values[63]	3469	1			T374	13		T449	53		T409	17
values[64]	26614	1			T374	156		T449	141		T409	145

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	610237	1			T66	8		T67	46		T72	8
values[2]	2541102	1			T66	42		T67	272		T72	975
values[3]	1158969	1			T66	263		T67	31		T72	298
values[4]	144656	1			T66	291		T67	2		T73	2
values[5]	73218	1			T66	219		T406	104		T388	10
values[6]	47416	1			T66	131		T406	89		T388	10
values[7]	34894	1			T66	90		T406	80		T388	10
values[8]	28152	1			T66	90		T406	66		T388	11
values[9]	23661	1			T66	70		T406	44		T388	10
values[10]	21002	1			T66	47		T406	47		T388	10
values[11]	18622	1			T66	33		T406	35		T388	10
values[12]	16807	1			T66	27		T406	28		T388	10
values[13]	15504	1			T66	16		T406	32		T388	10
values[14]	15073	1			T66	21		T406	27		T388	10
values[15]	13962	1			T66	21		T406	33		T388	10
values[16]	12952	1			T66	29		T406	22		T388	10
values[17]	12458	1			T66	23		T406	20		T388	10
values[18]	12108	1			T66	9		T406	19		T388	10
values[19]	11745	1			T66	16		T406	13		T388	11
values[20]	11500	1			T66	12		T406	19		T388	10
values[21]	11078	1			T66	12		T406	27		T388	10
values[22]	10063	1			T66	16		T406	35		T388	10
values[23]	9679	1			T66	13		T406	30		T388	10
values[24]	9764	1			T66	18		T406	22		T388	10
values[25]	9157	1			T66	15		T406	31		T388	11
values[26]	8774	1			T66	14		T406	12		T388	10
values[27]	8129	1			T66	11		T406	8		T388	10
values[28]	7699	1			T66	7		T406	11		T388	10
values[29]	7100	1			T66	15		T406	4		T388	10
values[30]	6910	1			T66	17		T406	8		T388	10
values[31]	6343	1			T66	7		T406	3		T388	11
values[32]	5816	1			T66	2		T406	3		T388	10
values[33]	5473	1			T66	3		T406	4		T388	10
values[34]	5029	1			T66	5		T406	6		T388	10
values[35]	4542	1			T66	1		T406	3		T388	10
values[36]	4391	1			T66	1		T406	3		T388	10
values[37]	4195	1			T66	1		T406	4		T388	10
values[38]	3946	1			T66	3		T406	5		T388	10
values[39]	3711	1			T66	2		T406	6		T388	10
values[40]	3575	1			T66	5		T406	4		T388	10
values[41]	3609	1			T66	2		T406	1		T388	10
values[42]	3497	1			T66	4		T406	1		T388	10
values[43]	3454	1			T66	1		T406	1		T388	11
values[44]	3455	1			T66	1		T406	1		T388	10
values[45]	3485	1			T66	2		T406	2		T388	10
values[46]	3375	1			T66	2		T406	3		T388	10
values[47]	3225	1			T66	1		T406	2		T388	10
values[48]	3220	1			T66	2		T406	2		T388	10
values[49]	3182	1			T66	1		T406	1		T388	11
values[50]	3011	1			T66	1		T406	1		T388	10
values[51]	2898	1			T66	1		T406	6		T388	10
values[52]	2884	1			T66	1		T406	1		T388	10
values[53]	2887	1			T66	1		T406	5		T388	10
values[54]	2887	1			T66	1		T406	1		T388	10
values[55]	2741	1			T66	1		T406	7		T388	10
values[56]	2614	1			T66	1		T406	1		T388	10
values[57]	2620	1			T66	4		T406	6		T388	10
values[58]	2622	1			T66	1		T388	10		T498	7
values[59]	2588	1			T66	6		T388	10		T498	2
values[60]	2613	1			T66	9		T388	10		T498	1
values[61]	2758	1			T66	7		T388	10		T498	1
values[62]	3873	1			T66	6		T388	10		T498	1
values[63]	18567	1			T66	21		T388	188		T498	8
values[64]	202762	1			T66	14		T388	1543		T498	77