Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1542177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

23044683

1

T1

18002

T2

54664

T3

4287

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15593698	1			T1	4510		T2	44694		T3	1420
values[0x0]	7844483	1			T1	13492		T2	9970		T3	2867
values[0x1]	1148679	1			T1	584		T2	2		T3	237

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	541484	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

24045376

1

T1

18586

T2

54666

T3

4524

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11259493	1			T1	9293		T2	27333		T3	2262
valid_sources[0x01]	11256692	1			T1	9293		T2	27333		T3	2262
valid_sources[0x02]	34352	1			T71	2		T68	195		T336	203
valid_sources[0x03]	32611	1			T494	39		T68	163		T336	142
valid_sources[0x04]	33500	1			T68	122		T336	214		T880	10
valid_sources[0x05]	33314	1			T68	197		T336	151		T880	5
valid_sources[0x06]	32521	1			T61	1		T254	1		T68	135
valid_sources[0x07]	33600	1			T68	194		T336	156		T880	3
valid_sources[0x08]	32861	1			T61	2		T68	169		T336	137
valid_sources[0x09]	33074	1			T71	7		T68	176		T336	181
valid_sources[0x0a]	33380	1			T61	2		T254	3		T68	136
valid_sources[0x0b]	33272	1			T61	1		T68	98		T336	186
valid_sources[0x0c]	33316	1			T68	127		T336	173		T880	11
valid_sources[0x0d]	33401	1			T61	1		T68	162		T336	124
valid_sources[0x0e]	33750	1			T61	1		T254	2		T68	211
valid_sources[0x0f]	33341	1			T254	1		T68	153		T336	176
valid_sources[0x10]	35147	1			T61	1		T68	160		T336	145
valid_sources[0x11]	33005	1			T68	199		T336	172		T880	10
valid_sources[0x12]	33433	1			T68	110		T336	90		T880	9
valid_sources[0x13]	34241	1			T61	1		T68	206		T336	173
valid_sources[0x14]	32828	1			T61	1		T71	1		T254	2
valid_sources[0x15]	33535	1			T254	4		T68	205		T336	152
valid_sources[0x16]	32927	1			T61	1		T68	164		T336	177
valid_sources[0x17]	34163	1			T254	1		T68	177		T336	200
valid_sources[0x18]	33078	1			T61	1		T254	1		T68	142
valid_sources[0x19]	33408	1			T254	3		T68	180		T336	179
valid_sources[0x1a]	33227	1			T71	2		T68	157		T336	178
valid_sources[0x1b]	33279	1			T61	3		T68	187		T336	99
valid_sources[0x1c]	33517	1			T68	196		T336	145		T880	7
valid_sources[0x1d]	33075	1			T254	1		T68	177		T336	176
valid_sources[0x1e]	33615	1			T61	1		T254	2		T68	190
valid_sources[0x1f]	33156	1			T61	2		T253	2		T254	1
valid_sources[0x20]	33318	1			T61	3		T254	1		T68	138

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15002138

1

T1

4510

T2

44694

T3

1420

values[0x0]

all_enables

biggest_size

7803702

1

T1

13492

T2

9970

T3

2867

values[0x1]

all_enables

biggest_size

238843

1

T61

18

T70

18

T71

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2792975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

440548

1

T66

257

T67

46

T72

134

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1096524	1			T66	568		T67	107		T72	331
values[0x0]	1042532	1			T66	579		T67	105		T72	346
values[0x1]	1094467	1			T66	538		T67	124		T72	358

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2161642	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1071881

1

T66

575

T67

110

T72

329

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50929	1			T66	25		T67	3		T72	43
valid_sources[0x01]	50138	1			T66	35		T67	7		T72	5
valid_sources[0x02]	50737	1			T66	22		T67	2		T72	2
valid_sources[0x03]	50334	1			T66	22		T67	3		T73	2
valid_sources[0x04]	50519	1			T66	27		T67	3		T72	29
valid_sources[0x05]	50467	1			T66	31		T67	6		T72	29
valid_sources[0x06]	52001	1			T66	21		T67	17		T73	3
valid_sources[0x07]	50384	1			T66	27		T72	17		T73	3
valid_sources[0x08]	50654	1			T66	27		T67	4		T72	21
valid_sources[0x09]	49366	1			T66	26		T67	5		T72	7
valid_sources[0x0a]	51301	1			T66	25		T67	7		T72	28
valid_sources[0x0b]	50981	1			T66	20		T67	8		T72	22
valid_sources[0x0c]	50597	1			T66	21		T67	4		T72	18
valid_sources[0x0d]	51361	1			T66	29		T67	6		T72	14
valid_sources[0x0e]	49987	1			T66	22		T67	2		T72	36
valid_sources[0x0f]	50376	1			T66	29		T67	2		T72	22
valid_sources[0x10]	49995	1			T66	31		T67	7		T72	9
valid_sources[0x11]	50113	1			T66	29		T67	6		T72	11
valid_sources[0x12]	50631	1			T66	26		T67	6		T72	17
valid_sources[0x13]	49662	1			T66	26		T67	19		T72	27
valid_sources[0x14]	51252	1			T66	16		T67	7		T72	41
valid_sources[0x15]	50899	1			T66	24		T67	4		T73	1
valid_sources[0x16]	51936	1			T66	20		T67	4		T73	3
valid_sources[0x17]	50072	1			T66	29		T67	4		T72	56
valid_sources[0x18]	50815	1			T66	19		T67	6		T72	20
valid_sources[0x19]	49530	1			T66	22		T67	1		T72	5
valid_sources[0x1a]	49338	1			T66	21		T67	5		T72	7
valid_sources[0x1b]	51406	1			T66	22		T67	8		T72	37
valid_sources[0x1c]	50713	1			T66	30		T67	5		T72	7
valid_sources[0x1d]	50370	1			T66	29		T67	6		T72	6
valid_sources[0x1e]	50067	1			T66	36		T67	4		T72	15
valid_sources[0x1f]	50010	1			T66	24		T67	3		T72	10
valid_sources[0x20]	49848	1			T66	28		T67	6		T72	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46272

1

T66

29

T67

9

T72

19

values[0x0]

all_enables

biggest_size

348203

1

T66

200

T67

35

T72

96

values[0x1]

all_enables

biggest_size

46073

1

T66

28

T67

2

T72

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2978873	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

483935

1

T66

277

T67

118

T72

145

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1185652	1			T66	656		T67	272		T72	380
values[0x0]	1091668	1			T66	605		T67	253		T72	358
values[0x1]	1185488	1			T66	639		T67	276		T72	377

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2286382	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1176426

1

T66

661

T67

270

T72

374

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54986	1			T66	19		T67	7		T72	21
valid_sources[0x01]	54170	1			T66	28		T72	12		T74	5
valid_sources[0x02]	54700	1			T66	31		T67	1		T72	24
valid_sources[0x03]	53771	1			T66	32		T67	20		T72	14
valid_sources[0x04]	54070	1			T66	26		T72	20		T73	2
valid_sources[0x05]	53909	1			T66	24		T67	15		T72	13
valid_sources[0x06]	54885	1			T66	29		T67	31		T72	26
valid_sources[0x07]	53297	1			T66	31		T67	11		T72	19
valid_sources[0x08]	54506	1			T66	26		T72	17		T73	2
valid_sources[0x09]	54189	1			T66	30		T67	15		T72	22
valid_sources[0x0a]	54229	1			T66	34		T67	14		T72	14
valid_sources[0x0b]	53572	1			T66	25		T72	27		T73	1
valid_sources[0x0c]	54002	1			T66	40		T67	7		T72	10
valid_sources[0x0d]	54251	1			T66	34		T67	7		T72	18
valid_sources[0x0e]	54531	1			T66	44		T67	4		T72	8
valid_sources[0x0f]	53272	1			T66	29		T67	12		T72	31
valid_sources[0x10]	53583	1			T66	32		T67	10		T72	12
valid_sources[0x11]	54801	1			T66	22		T67	18		T72	18
valid_sources[0x12]	54876	1			T66	18		T67	24		T72	18
valid_sources[0x13]	54099	1			T66	25		T67	17		T72	19
valid_sources[0x14]	54026	1			T66	24		T67	1		T72	19
valid_sources[0x15]	53967	1			T66	31		T72	18		T406	200
valid_sources[0x16]	54763	1			T66	26		T72	12		T73	2
valid_sources[0x17]	54141	1			T66	38		T67	16		T72	20
valid_sources[0x18]	53988	1			T66	30		T67	7		T72	18
valid_sources[0x19]	53604	1			T66	34		T72	9		T73	2
valid_sources[0x1a]	54728	1			T66	28		T67	10		T72	12
valid_sources[0x1b]	53626	1			T66	19		T72	12		T73	1
valid_sources[0x1c]	53533	1			T66	39		T67	7		T72	18
valid_sources[0x1d]	54050	1			T66	36		T67	5		T72	18
valid_sources[0x1e]	53882	1			T66	17		T67	9		T72	16
valid_sources[0x1f]	54171	1			T66	31		T67	4		T72	17
valid_sources[0x20]	53454	1			T66	33		T67	22		T72	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50660

1

T66

27

T67

9

T72

10

values[0x0]

all_enables

biggest_size

382232

1

T66

224

T67

98

T72

121

values[0x1]

all_enables

biggest_size

51043

1

T66

26

T67

11

T72

14

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2820163	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

446219

1

T66

211

T67

55

T72

170

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1106615	1			T66	580		T67	115		T72	404
values[0x0]	1053109	1			T66	556		T67	111		T72	408
values[0x1]	1106658	1			T66	581		T67	117		T72	469

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2183195	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1083187

1

T66

589

T67

128

T72

429

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51626	1			T66	38		T67	5		T72	17
valid_sources[0x01]	51774	1			T66	41		T67	5		T72	19
valid_sources[0x02]	51548	1			T66	22		T67	4		T72	27
valid_sources[0x03]	50449	1			T66	29		T67	4		T72	19
valid_sources[0x04]	51254	1			T66	17		T67	4		T72	22
valid_sources[0x05]	50883	1			T66	23		T67	5		T72	13
valid_sources[0x06]	51112	1			T66	27		T67	24		T72	14
valid_sources[0x07]	50599	1			T66	28		T67	2		T72	18
valid_sources[0x08]	51444	1			T66	33		T67	4		T72	18
valid_sources[0x09]	50444	1			T66	21		T67	2		T72	21
valid_sources[0x0a]	50577	1			T66	26		T67	9		T72	19
valid_sources[0x0b]	50546	1			T66	22		T67	3		T72	15
valid_sources[0x0c]	50835	1			T66	34		T67	3		T72	25
valid_sources[0x0d]	51771	1			T66	26		T67	2		T72	26
valid_sources[0x0e]	50313	1			T66	43		T67	5		T72	21
valid_sources[0x0f]	51744	1			T66	22		T67	4		T72	14
valid_sources[0x10]	50938	1			T66	15		T67	1		T72	21
valid_sources[0x11]	51451	1			T66	29		T67	2		T72	21
valid_sources[0x12]	51841	1			T66	11		T67	11		T72	23
valid_sources[0x13]	50950	1			T66	13		T67	13		T72	15
valid_sources[0x14]	51305	1			T66	27		T67	2		T72	21
valid_sources[0x15]	50605	1			T66	54		T67	3		T72	16
valid_sources[0x16]	51333	1			T66	19		T67	6		T72	14
valid_sources[0x17]	51288	1			T66	38		T67	5		T72	19
valid_sources[0x18]	51371	1			T66	21		T67	5		T72	31
valid_sources[0x19]	50360	1			T66	18		T67	5		T72	13
valid_sources[0x1a]	49918	1			T66	31		T67	1		T72	25
valid_sources[0x1b]	50867	1			T66	35		T67	4		T72	22
valid_sources[0x1c]	51371	1			T66	17		T67	2		T72	21
valid_sources[0x1d]	51377	1			T66	28		T67	2		T72	24
valid_sources[0x1e]	50567	1			T66	23		T67	5		T72	16
valid_sources[0x1f]	51497	1			T66	34		T67	8		T72	19
valid_sources[0x20]	50316	1			T66	11		T67	6		T72	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47112

1

T66

18

T67

11

T72

15

values[0x0]

all_enables

biggest_size

352285

1

T66

174

T67

40

T72

136

values[0x1]

all_enables

biggest_size

46822

1

T66

19

T67

4

T72

19